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An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is...
A CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption while retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only 12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-mum CMOS technology. An analog behavior...
A quad-band GSM/GPRS/EDGE receiver front-end including I and Q ADCs designed in 90nm digital CMOS technology is presented. The low band receiver designed for GSM850/GSM900 achieves 33dB gain, 1.9dB noise figure, 7.5dB of noise figure under blocking condition and -20dBm of in-band IIP3 with a power of 68mW, while the high band DCS/PCS receiver achieves 32dB gain, 2.2dB noise figure, 9.3dB of noise...
In this paper, we present a method to reduce the effects of substrate noise on bandpass sigma-delta (SigmaDelta) ADCs through the use of band-stop noise modulation, where the notch of the modulation noise spectrum is centered around the input signal band. Several band-stop noise (BSN) resonator structures required for bandpass SigmaDelta ADC implementations are presented. The proposed designs have...
This paper presents a circuit and a design of a CMOS zero cross-conduction low-power driver for an integrated synchronous buck converter. The circuit has a zero cross-conduction, yielding low-power dissipation and high efficiency. We used the Cadence design tool with 0.18 mum CMOS technology to implement and verify the functionalities of the low-power buck converter driver. The design criteria of...
We present an efficient approach for on-chip frequency response measurement, including phase and gain, of analog circuitry in mixed-signal systems. The approach uses direct digital synthesizer (DDS) to supply test sine waves with different frequencies and phases. The output response is analyzed using a multiplier and accumulator. The resultant phase delay measurement is used to correct other measurements...
The bifurcation analysis of a second-order continuous-time forest-fire impact model is carried out by resorting to a properly defined one-dimensional discrete-time system (map). The map is derived quite directly from the forest-fire model and is exploited to find out the regions of the chosen parameter domain characterized by qualitatively different behaviors. The results are compared with the bifurcation...
In contrast to most of the clinical examinations, the sonotubometric assessment of the Eustachian tube function allows the registration of the tube opening at the perforated, as well as at the intact eardrum in physiological conditions. In this paper, a new procedure is introduced which performs a measurement of the transmission path nose/ear. With digital signal processing algorithms the generation...
An optimization approach for the design of fractional delay (FD) FIR filters based on a genetic algorithm (GA) is presented. The approach exploits the advantages of a global search technique to determine the coefficients of an FD FIR filter based on the Farrow structure. The proposed approach involves a binary encoding scheme and a multiobjective error formulation based on the amplitude response and...
A major disadvantage of image retrieval systems is their lack of objects orientation and scaling matching. This paper addresses the issue of accurate, effective, computationally efficient, fast and fully-automated 2D object orientation and scaling determination. The approach relies on the objects frequency-based features. The frequency-based features used by the proposed technique, are extracted by...
In this paper, we propose a blind frame-by-frame dereverberation using correlation coefficients considering periodicity of voiced speech. In the proposed method, the reference signal is derived by reducing speech periodicity from recovered signal of previous frame. The reference signal is used in order to estimate the impulse response in each frame. The recovered signal is obtained by using the estimated...
According to former results from (Dittmann et al., 2005) in this paper we summarize the design principles from the general approach and introduce extended experimental test results of a voice-over-IP (VoIP) framework including a steganographic channel based on (Dittmann et al., 2005), (Dittmann and Hesse, 2004), (Kraetzer et al., 2006) and (Vogel et al., 2006). We show that using this framework it...
This paper describes a sampled analog architecture for computing 2D DCT of an 8 times 8 image block using switched capacitor principle, with capacitance switching. The input sample stream is applied to a bank of capacitors and multiplied by all the deduced 2D DCT coefficients simultaneously using capacitor ratios. These capacitors are switched concurrently with the help of a switching matrix, to realize...
In this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage to require information well known by designer, simple and easy to apply even for complex circuits. With only the knowledge of the input signal spectrum and the transfer function from...
In this paper, a low power mechanism with power block management is proposed to reduce the power consumption in DSP chips. Because the digital signal processing (DSP) chips use many functional units in the data-path to achieve parallel processing, the unnecessary functional units are also executed simultaneously, and they dissipate the power. In the paper, we classify the types of instruction sets...
In this paper, we use the minimum mean square error (MMSE) criterion to design the scaled and offset belief propagation (BP)-based decoding algorithms for short low-density parity-check (LDPC) codes on the fast Rayleigh fading channel. Based on the MMSE criterion, the theoretical formulas and numerical calculations on the optimum factors for these two improved BP-based algorithms are provided. The...
In this paper, the performance of an exponentially modulated filter bank based multicarrier (FBMC) modulation is compared with a cyclic prefix based OFDM (CP-OFDM). Both frame and bit error rates (FER/BER) are evaluated using the ITU-R vehicular-A channel model and LDPC forward error correction coding. For FBMC, a low complexity per-subcarrier equalizer called AP-ASCET is utilized to perform channel...
As a promising approach to mitigate the challenge of interconnect limit, X-architecture allows routings along diagonal directions in addition to rectilinear directions. It can reduce routing wire length and vias number compared with conventional Manhattan routing. Although Steiner minimum tree and signal routing algorithms have been developed for X-architecture, clock routing has not been addressed...
Energy consumption is one of the most critical constraints in the current VLSI system designs. In addition, fault tolerance of VLSI systems is also one of the most important requirements in the current shrunk VLSI technologies. This paper presents low power and fault tolerant bus encoding methods considering coupling effects of bus interconnects. Experiments using SPEC2000 benchmark programs show...
Fast Fourier transformation (FFT) and its inverse (IFFT) are used in orthogonal frequency division multiplexing (OFDM) systems for data (de)modulation. The transformations are the kernel tasks in an OFDM implementation, and are the most processing-intensive ones. Recent trends in the electronic consumer market require OFDM implementations to be flexible, making a trade-off between area, energy-efficiency,...
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