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In this paper, given a set of timing-driven routing trees for all the interconnection nets, a new multilevel timing-constrained full-chip routing (MTFR) in a dynamic hierarchical quad-grid model is proposed to complete full-chip routing in reasonable time. The experimental results show that the proposed MTFR approach uses less CPU time to obtain 100% timing-constrained routing results for all the...
This paper presents a novel video compression system with a low complexity encoder. Based on the Slepian-Wolf theorem and the Wyner-Ziv theorem, a video is intraframe coded and interframe decoded in this system. The system performance, the compression rate and the video quality, is affected by the difference between the source information and the side information. To increase the accuracy of the side...
In this paper we demonstrate that an intrinsic amplitude detector exists in negative resistance CMOS LC oscillators. The DC bias on the common-mode node in CMOS VCOs depends on the oscillation amplitude. Amplitude control loops can thus be built without a separate amplitude detector. Insights in possible AM to PM noise mechanisms are also derived
Recently, we have shown the emergence of oscillatory behaviour in unforced bistable systems having dynamics of the general form: tx equiv partU(x,t)/partx, subject to carefully crafted coupling schemes. Here, we present experimental results obtained on a physical system implemented with N=3 coupled ferromagnetic cores; the oscillatory behaviour is triggered when the coupling constant exceeds a threshold...
A simple technique to evaluate the linearity performance of a tunnel diode oscillator is presented. The approach is based on the phasor method and avoids redundant computations and/or iterations required by traditionally adopted mathematical tools. Equations found are simply derived, extend our knowledge on harmonics generation and are particularly useful for the designer. A design example is provided...
H.264 defines 7 different coding modes for macroblocks (MBs) in P slices. In order to achieve a coding performance as high as possible, the H.264 encoder calculates rate distortion costs of all possible modes to determine the best mode of a MB. The computation complexity is so large that make it difficult to be used in practical applications especially in real time environment. In this paper, a fast...
Network synchronization of flat multihop ad hoc networks is considerably different from conventional systems that are usually hierarchically organized. Lately, connected dominating sets (CDSs) are used in ad hoc networks to structure even larger scaled topographies into smaller portions. While these virtual infrastructures are initially utilized for efficient flooding or routing purposes, this paper...
In this paper, we present a robust multiuser detector for wireless multicarrier code-division multiple access (MC-CDMA) systems under time-varying narrowband interference (NBI). The conventional least-squares (LS) channel estimators and multiuser detectors will perform poorly when narrowband interfering signals contaminate the multicarrier systems. A new weighted least M-estimate (WLM) multiuser detector...
Utilizing an on-chip decompressor is an efficient method to reduce test data volume in multiple-scan-chain designs. This paper investigates a new technique to implement the decompressor by combinational circuits. The proposed architecture drives a large number of internal scan chains with far fewer external input pins, thus delivering significant reductions in test data volume. Based on the analysis...
This research presents a test-bench implementation of a novel debug support system that targets the needs of hard real-time embedded systems. The solution provides over 70 percent combined program and data trace compression using a low complexity messaging framework and subtraction based differential compression. The test-bench is based on an open source multi-processor system-on-chip design, where...
The binarization stage is a very critical in document analysis since the quality of a binarized image determines the performance of the entire process. However due to many uncertain factors such as complex signal-dependent noise and variable background intensity, which is caused by non-uniform illumination, shadow, smear, smudge or low contrast, an effective binarization algorithm that will work on...
It is shown that synchronization is similar to amplitude stabilization: both mechanisms involve creation of harmonics and frequency reduction. Synchronization of LC-oscillators can be achieved using similar synchronizing circuits in each oscillator connected in parallel with the tank. The output of the first synchronization circuit is routed to the second oscillator and vice versa. This scheme provides...
This paper presents a system-level verification algorithm using the Petri net theory to detect design errors for high-level synthesis of dataflow graphs. Typically, given a dataflow graph and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-level synthesis becomes a key issue...
Digital compensator design is an important and essential step to achieve stable power converter with good steady-state and dynamic performance. Generally there are two digital controller design approaches: The digital redesign approach and the direct design approach. In this paper, hybrid discretization (s-to-z transformation) approach is applied to power converters digital controllers/compensators...
In order to improve the downlink capacity of a multiuser multiple input multiple output system exploiting spatial multiplexing, this paper proposes two grouped multiuser diversity schemes. Aiming at the suppression of co-channel interference, both schemes select a group of users to share the same time-frequency channel unit in two steps. The first scheme iteratively selects the users based on a traditional...
An analysis of reflective-type phase shifters with transformed single-resonant loads is presented. Several components of the standard lumped-element coupler can be eliminated without significant performance degradation, to allow more compact implementations. A reflective-type phase shifter operating at 2.0 GHz has been designed in a 0.18 mum CMOS process, occupying an area of 0.75 mm2 and consuming...
This paper investigates the performance of passive and active inductors for digital Si-CMOS technologies. The extreme low-resistivity of the Si-substrate and the absence of thick top metal layers in digital-CMOS processes prevent the implementation of high-Q passive inductors, and demand alternate solutions. A detailed comparison between the active and passive inductors based on several performance...
The so called "super-exponential" methods (SEMs) are attractive methods for solving multichannel blind deconvolution problem. The conventional SEMs, however, have such a drawback that they are very sensitive to Gaussian noise. To overcome this drawback, the robust super-exponential method (RSEM) was proposed for single-input single-output infinite impulse response (SISO-IIR) channels and...
We propose a new method for solving the underdetermined sparse signal separation problem. Some sparseness based methods have already been proposed. However, most of these methods utilized a linear sensor array (or only two sensors), and therefore they have certain limitations; e.g., they cannot separate symmetrically positioned sources. To allow the use of more than three sensors that can be arranged...
Modified-DFT (MDFT) filter banks permit subchannels with linear phase characteristics, and provide high degrees of computational efficiency. However, in MDFT filter banks with subchannels exhibiting narrow transition-bandwidths, the length of the prototype filter becomes prohibitively long, reducing the computational efficiency. It is well known that the frequency-response masking (FRM) technique...
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