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A technique to reduce close-in phase noise in CMOS LC voltage controlled oscillators is proposed. In CMOS differential LC oscillators, the up-conversion of flicker noise mainly determines the close-in phase noise. The flicker noise of the bias current is a major component contributing to the overall low frequency noise. In this paper, a switched biasing technique to suppress the flicker noise of the...
A fully integrated 5-6GHz differential VCO derived from the classical Clapp topology is presented in 180nm CMOS. The Clapp architecture and its characteristics are reviewed, and the location of critical portions of the circuit such as the LC-tank and varactors is discussed. The use of a Clapp VCO topology allows a larger voltage swing, which improves spectral purity and phase noise. The use of a symmetrical...
This paper describes a high speed current mode multilevel simultaneous bi-directional I/O which calibrates pin-to-pin current mismatch. Output impedance is controlled by an impedance matching circuit reducing process variation down to plusmn2.5%. Maximum 20% pin-to-pin current mismatch is reduced to 1.25% by 4-bit digital calibration scheme. Simulation results based on 0.18mum CMOS process show that...
A method of direct input reference feedforward compensation is proposed and discussed for all digital phase locked loop based synthesizers. The practical issues in implementing the system are addressed, and analysis of the feedforward estimation error on the system is performed. A sample model was created and simulated. Simulation shows the effect of the feedforward estimation error on the system's...
This paper presents a new harmonic filtering technique to lower the phase noise of CMOS LC voltage-controlled oscillator (VCO) based on loaded-Q improvement approach. A single resistor was used at the drain node of the bias transistor instead of extra inductors and capacitors. The wide-band nature of resistance can suppress the second harmonic as well as other even harmonics leaking from the LC tank...
A 3.0 V 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC is presented. The ADC adopts a modified 1.5-bit/stage and multi-bit/stage pipelined architecture for low power consumption and small die area. The proposed operational amplifier with low parasitic capacitance reduces the power consumption and die area. This ADC achieves better than 56.3dB SDNR at 100 MSample/s for a 100MHz input frequency....
The finite field is widely used in error-correcting codes and cryptography. Among its important arithmetic operations, multiplication is identified as the most important and complicated. Therefore, a multiplier with concurrent error detection ability is elegantly needed. In this paper, a concurrent error detection scheme is presented for bit-parallel systolic dual basis multiplier over GF(2m). The...
A mesochronous pipeline architecture is described in this paper. Significant performance gains are possible with mesochronous pipeline over conventional pipeline architecture. The clock period in conventional pipeline scheme is proportional to the maximum stage delay while in mesochronous pipelining it is proportional to the maximum delay difference, which means higher clock speeds are possible in...
This paper presents some results on absolute stabilization of nonlinear discrete-time systems under control saturations. The studied control law consists of the feedback of both the states and of the nonlinearity present in the dynamics of the controlled system. Saturations are taken into account by modelling the nonlinear saturated system through deadzone nonlinearities satisfying a modified sector...
This paper proposes a FIR-RAKE receiver algorithm that makes use of a pilot signal broadcast by the TD-SCDMA (time division-synchronous code division multiple access) base station to obtain channel parameter estimates in the downlink of TD-SCDMA wireless network. The algorithm can reduce multipath interference for the mobile units and with lower complexity of FIR implementation, where only one marching...
An automatic synthesis tool for RFIC design is demonstrated. The tool incorporates built-in numerical simulators for fast evaluation of the performance metrics. Nonlinearity is modeled using Volterra series method. The tool additionally provides the dimensions of the on-chip inductors along with their values. To validate this approach, a low noise amplifier (LNA) at 900MHz is synthesized using a 0...
This paper and its companion paper (entitled Part II - algorithm) together present techniques for low power realization of finite impulse response (FIR) filters using improved differential coefficients method (DCM). This paper presents the necessary foundation and terminology of the DCM. The companion paper describes our algorithm and presents design examples. In contrast to the conventional DCM that...
This paper extols the virtues of information theoretic approach to the synthesis of reduced multirooted directed acyclic graph (DAG) representation for the multiplier block of FIR filters. The proposed maximum likelihood decomposition algorithm can be viewed as an efficient divide-and-conquer approach with dynamic tracking of the statistic of weight-two subexpressions. As isomorphic subgraphs of the...
In the paper, easy and smart algorithm for FIR filter coefficients quantization is presented. In the first step digital FIR filter coefficients are computed using any method known from literature. In the next step filter polynomial is factored and the filter is transformed into two cascaded FIR sections. Coefficients of the first section are quantized. In the article, simple optimal quantization method...
In this paper, we introduce a symbolic tool able to characterize the basic elements of a piezo-electromechanical structure. This tool gives us the opportunity to develop a useful procedure for investigating the properties of the whole electromechanical system and, in particular, the non-ideal behavior of the RC-active network connected to the structure. The main goal of this procedure is to determine...
This work analyzes different parameter extraction methods for on-chip integrated inductors and assesses and their impact on inductor design. The relationship between extracted single-ended and differential parameters is investigated through the use of theoretical network models that support the calculation equations. Experimental results from a test chip are presented and a lumped model, which adequately...
This paper tackles the problem of accelerating motion estimation for video processing. A novel architecture using binary data is proposed, which attempts to reduce power consumption. The solution exploits redundant operations in the sum of absolute differences (SAD) calculation, by a mechanism known as early termination. Further data redundancies are exploited by using a run length coding addressing...
Wavelet-based image denoising can be extended to a video by applying it to each video frame independently. The denoising performance can be improved by exploiting inter-frame correlations, for example, using appropriate temporal filtering. However, fixed temporal filters might not perform sufficiently well due to their inability to cope with the variability of inter-frame correlations across the video...
This paper proposes a new algorithm for H.264 rate control. First, we estimate the frame target bit based on the proportional-integral-derivative (RAPID) buffer control to avoid the buffer overflow or underflow. With the frame target bit, we use the quadratic R-D model to estimate the frame quantization parameter (QP). Finally, we apply Kalman filter to further dynamically adjust macroblock QP to...
This paper describes the implementation of a bio-inspired six legged robot: Gregor I. Both structure and locomotion control are inspired by biological observations in cockroaches. Robot mechanics attempts to emulate main structural features in cockroaches, like self-stabilizing posture and specializing legged function; in turn, locomotion control is based on the theory of the central pattern generator...
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