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A study on measurement configurations for the estimation of power consumption of processing systems is presented in this work. The problem addressed is to measure the energy that a digital system consumes for a numerous number of clock cycles and to assign this consumption to a specific group of instructions. This kind of energy measurement provides the information for determining the energy consumption...
In this paper, a new architecture of distributed embedded memory cores for SoC is proposed and an effective memory repair method by using the proposed spare line borrowing (software-driven reconfiguration) technique is investigated. It is known that faulty cells in memory core show spatial locality, also known as fault clustering. This physical phenomenon tends to occur more often as deep submicron...
The subject paper proposes developing test environment and test methodologies for digital embedded cores-based system-on-a-chip (SOC). The digital cores used in the study were constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be IEEE P1500-compliant. The test access mechanism plays an important...
An embedded test stimulus decompressor is presented to generate the test patterns, which can reduce the required vector memory and channels of automatic test equipment (ATE). The decompressor consists of a periodically alterable MUX network which has multiple configurations to decode the input information flexibly. A complete synthesis flow is presented to generate the MUXs network automatically....
This paper introduces a novel architecture that is targeted for adaptive embedded system applications, such as telerobotics, space navigation and wireless hot-spot access points. All these applications consist of static (i.e. known) hard and soft realtime constraints, as well as dynamic (i.e. unknown and unpredictable) environment conditions, hence require the predictability of fixed hardware resources,...
Commercial off the shell (COTS) software/hardware and standalone instruments were used to study the feasibility of the development of a QAM evaluation system to support developments of components/sub-systems for high data rate digital communication. Once the concept was proven it was transferred from a rack-and-stack configuration to a standalone test system including its own circuitry and embedded...
Indirect measurement architecture for speed estimation has been presented in this paper. This system is based on neural estimator implemented on programmable system on-chip (PSoC), using C++ language, which executes speed estimator algorithm, considering a 1.0 s time interval for neural estimator. The results from experiments and simulations indubitably proved the proposed estimator good performance...
Since an embedded circuit board is lower in cost, smaller in size, and lower in power consumption than a PC. In this paper, we use an integrated embedded circuit board instead of using a PC and interface circuit board with our system, which can provide the ECG measurement of a patient who is outside of a hospital. The collected medical information through computer networks are stored in the medical...
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