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In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal...
The wireless Internet will introduce revolutionary new applications that pave the way toward a mobile information society. Third generation mobile communication systems and broadband wireless access systems will play the key role in enabling wireless Internet. Because of rapidly increasing system complexity, wireless terminal manufacturers face huge challenges in ensuring fast product creation. In...
A charge offset scanning method of determining individual cell leakages in DRAM devices is described. The leakage behaviour of cells from the main and tail distributions is compared and the results of data retention studies on a 0.5µm CMOS embedded DRAM technology for ASIC applications are also discussed. An order of magnitude improvement in the retention time of the tail bits was achieved as an outcome...
On-chip shared-cache memories with high access-bandwidth are desirable for single-chip processors with parallel execution capability of multiple instructions. For this application a new area-efficient hierarchical architecture [1,2] is ideally suited, because the necessary large storage capacities as well as sufficiently low power consumption can be realised in addition to the high access-bandwidth...
A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate...
We present a monolithically integrated high IP3 RF receiver chip set for mobile radio base stations up to 2 GHz, in a 25 GHz fTSi bipolar production technology. The chip set consists of a RF preamplifier, an active mixer and an IF limiter. The preamplifier gain is 12dB, the noise figure is 5.5 dB and the IP3OUTis +24 dBm at 900 MHz. The mixer conversion gain is 1.5 dB, the IP3OUTis +26 dBm and the...
This paper presents a CMOS integrated circuit, to be used as pre-filter in video systems. The circuit is a lowpass switched capacitor decimation filter, based on the polyphase decomposition of the transfer function in structurally all pass sections. The filter presents low sensitivity to transfer function coefficient errors and low power consumption.
A technique for low-distortion and digitally programmable continuous-time filtering is proposed. Digital controllability is based on an inherent linear MOST-only current division technique. This technique is applied to achieve a VGA with gain from -10 dB to 53 dB in steps of 1 dB and with linearity better than -80 dB. The filter is a 5th order Butterworth low-pass with ± 50% tuning range around 1...
This paper presents a 7th order polyphase (14th order bandpass) gm-C IF filter implemented in a 0.35 µm CMOS process. The filter bandwidth is 1 MHz, the center frequency is 3 MHz, the image band rejection is higher than 53 dB, the stop band attenuation is at least 40 dB, and the in-band group delay variation is 0.5 µs. The noise floor is 170 µVrmsand the spurious free dynamic range is at least 59...
A new I/Q demodulator based on a combined Hilbert sampler/filter and complex bandpass switched-capacitor (SC) filter is presented. The test circuit subsamples a 45 MHz IF signal to a new, lower IF of 13 kHz. The circuit achieves image rejection of over 50 dB on a 24 kHz bandwidth.
Based on a conventional successive approximation ADC architecture a new and faster solution is presented. The input structure of the new solution consists of transmission gates and capacitors only and there is no need for any active element. A switching circuit is implemented to allow a wider input voltage range of the ADC. Together with a self timed comparator the power consumption is noticeably...
Since most CMOS imagers read out large pixel sets (e.g. lines) at the same time, we can choose a level of parallelism to do analog to digital conversion (ADC). This paper presents the design, simulation and measurement results of a 10 bit fully parallel ADC in a 0.35µ process, taking 1 mm2and 7 mW to convert 50 VGA images per second.
This paper reports a 1-V, 3.44-ns, 4.1-mW at 50MHz, 128- Kb, four-way set-associative CMOS cache memory implemented by TSMC 1.8V 0.18µm foundry CMOS technology for low-voltage low-power VLSI system applications. Owing to the distributed tag sense-amps with a dynamic logic control, the 10-T tag cell with the built-in tag compare capability, and the dynamic pulse generators for realizing read enable...
An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit 2-stage pipelined algorithmic analog-to-digital converter. At a sampling rate of 13 Msamples/s, the peak signal-to-noise-and-distortion ratio (SNDR) is 45 dB, and the spurious-free dynamic range (SFDR) is 60 dB. The total power dissipation is 23 mW from 3.0V. The active analog area is 0.11 mm2. The...
Based on the study about the previously developed back-bias generators, a new high-efficiency back-bias generator with the Cross-coupled Hybrid Pumping Circuit 2 (CHPC2) is presented in this paper. CHPC2 takes only the advantages from the previous ones, throwing away the disadvantages. CHPC2 shows |VBB|/VCCas large as 98% even at low VCC=0.9 V, strongly addressing that it will be suitable at low voltage...
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