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This paper presents a CMOS 0.8µm mixed-signal half-duplex MODEM ASIC for data transmission on the low-voltage power line. This circuit includes all the analog circuitry needed for input interfacing and modulation/ demodulation (input amplifier, PLL-based frequency synthesis, slave filter banks with PLL master VCO for tuning, and decision circuitry) plus the logic circuitry needed for control purposes,...
This paper examines the effect of the choice of MOS varactor on the performance of a CMOS negative resistance oscillator. The three most common MOS varactor structures (inversion, accumulation, and gated varactor) are combined with a spiral inductor over either deep trench oxide or a polysilicon patterned ground shield, to implement a matrix of six LC VCO's in a 0.24-µm (0.18- µm Leff) SiGe BiCMOS...
An integrated receiver channel with a wide dynamic range for a pulsed time-of-flight (TOF) laser rangefinder has been designed and tested. The circuit uses leading edge timing discrimination. The bandwidth of the receiver channel is 250 MHz and the maximum transimpedance 40 kΩ. The single-shot distance measurement accuracy is 65 mm, taking into account walk error (input signal amplitude varies in...
A fully integrated VCO with quadrature outputs for Zero- or Low-IF DCS1800, DECT or GSM receivers is presented. At 2.5V supply voltage and a power dissipation of 20mW, the VCO features a very low phase noise of -128dBc/Hz or better at 600kHz frequency offset over the tuning range, thus fulfilling more than the tough GSM-specifications. The oscillator is tunable from 1.71GHz to 1.99GHz and has a differential...
Regulated cascode (RGC) techniques are applied to achieve better isolation of the large input parasitic capacitance in a front-end preamplifier for optical receiver applications, since the RGC circuit behaves like a common-gate transistor with large transconductance comparable to GaAs MESFET. The input resistance of the RGC circuit becomes smaller by the amount of the voltage-gain of the local feedback...
A 10-bit 200 MS/s parallel pipeline ADC is presented. It consists of a front-end sample-and-hold circuit and four parallel pipelined component ADCs followed by a digital offset compensation. By incorporating double sampling both in the S/H circuit and the component ADCs a power dissipation of only 280 mW from a 3.0 V supply is achieved. The circuit is implemented with a standard 0.5 µm CMOS process...
A 0.25µm 2.5V CMOS analog front-end IC for an ADSL system is presented. The IC contains all analog functions including gain-controlled transmit and receive amplifiers, highly linear continuous-time low pass filtering including on-chip automatic tuning, 8.8Ms/s ADC and DAC as well as a crystal driver and a DAC-controlled VCO. The IC has been realized in a mixed-signal 0.25µm triple-well CMOS technology,...
In this paper, we present a noise-immune high-performance static circuit family called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and they are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power and dynamic noise immunity. Comparison...
This paper describes a new structure for Digital Controlled Oscillator Phase Locked Loops (DCOPLL) with fine quantization of the phase information, generic digital loop filter and digitally controlled crystal oscillator. It is particularly suited for applications in which high frequency resolution and low jitter are requested. The way in which the phase information is finely quantized allows the designer...
A two-stage stacked high IIP3 LNA with low current consumption is presented. Low-impedance bias terminations and optimum inter-stage match are used for IIP3 enhancement. A new graphical design technique is introduced for optimising the linearity trade-offs in two-stage amplifiers and for optimising the on-chip interstage matching network. Also, novel active circuits for bias modulation suppression...
A new simple on-chip regulated voltage-down-converter (VDC) is presented. The VDC output can be advantageously fixed at 2.5V, 3V or 3.5V. The voltage down converter was fabricated in 0.5µm CMOS technology from STMicroelectronics. The circuit provides a typical 3V output with a temperature dependency of only 300µV/°C. At 10mA loading current, the output is always stabilised within ±10% with 4V∼10V...
A low-ohmic substrate 0.25µm CMOS process has been chosen to carry out experiments to measure the effects of substrate noise on the performance of circuits operating at radio frequencies. Clock circuits give rise to substrate noise with spectral harmonics far into the RF band. These harmonics are injected into the signal path of RF circuitry as will be demonstrated. Clock planning is therefore a major...
A novel extraction method of high frequency small-signal model parameters for MOSFETs is proposed. From S-parameter measurement, this technique accurately extracts the model parameters including the charge conservation capacitance parameters. To consider charge conservation, nonreciprocal capacitance is considered. The modeled parameters fit the measurements very well without any optimization. The...
This paper discusses the impact and aspects on analog IC for wideband radio systems and in particular software defined radio. The strong evolution of digital ASIC's and signal processing cause analog IC and dataconverters to be bottlenecks of future radio systems. Signal dynamic range and linearity of dataconverters, frequency converters and power amplifiers are already today a great challenge. The...
This paper presents an electronic attenuator for audiometric applications, including an on-chip power amplifier which drives 8 Vppon a 7Ω resistive load. The 24 mm2chip, fabricated in a 2 µm high-voltage CMOS process, achieves 147 dB of dynamic range and 80 dB of signal-to-noise ratio, consuming 33 mA from a ±5 V power supply.
A new generation of Contactless Smartcard Chip is described. The Contactless Smartcard Chip integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous Quasi Delay Insensitive (QDI) 8-bit micro-controller. Beyond the contactless smartcard application field, this new chip demonstrates that System-on-Chip...
A low stress 1-GHz 0.25µm CMOS power amplifier intended for Linear Amplification with Non-linear Components(LINC) transmission is presented. The class-D output stage is partially soft-switched with a stacked pseudoclass-E pre-amplifier driver for increased efficiency. Operating from a 2.5V supply, the amplifier achieves a 50% Power-Added Efficiency(PAE) with a 1-GHz CW signal at a peak output power...
A parameterizable architecture of a low power FIR interpolation filter with reconfigurable coefficient sets for timing phase alteration is presented. For the application in a handheld ultrasound scanner, the filter has been optimized for lowest power dissipation on all levels of CMOS design from system down to physical layout level. The architecture is well suited for a datapath generator design offering...
A reduced voltage swing is often used to save power on interconnects. We investigate what is the optimum voltage swing for minimum power in different situations. This is done by modelling power versus voltage swing of the driver-interconnect-receiver combination, and look for the minimum of this power consumption. The results are illustrated by examples from a 0.18 µm CMOS process.
An integrated GSM compliant 2.7V, 900MHz/1.9GHz dual band transceiver with an I and Q interface including a dual integer N synthesizer is presented. The receiver provides a total of 110dB of gain range with 80dB of programmable gain range at IF selectable in steps of 2dB and 30dB of programmable gain range in the baseband selectable in steps of 10dB. An on-chip track and hold based DC offset correction...
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