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A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. A stochastic time-to-digital converter (STDC) with an edge-interchange circuit (EIC) is proposed. The rising edges of the two input clocks of STDC are cyclically interchanged by EIC, which achieves dynamic element matching and doubles the equivalent number of arbiters in STDC. The frequency resolution of the $LC$...
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