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This paper presents the design and chip-on-board packaging of a high-linearity four-element phased-array receiver for 9–10-GHz applications. The phased-array is built using 0.13- m CMOS with a single-ended design, and it results in a measured gain of 10.1 dB, an input of 12.5 dBm, an input of 4 dBm, and a noise figure of 3.4 dB at 9.5 GHz. An rms gain error...
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