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The Design Security Rule Check (DSeRC) framework is a first step toward automating the analysis of integrated circuit design vulnerabilities. By mathematically modeling vulnerabilities at each abstraction level and associating them with metrics and rules, DSeRC aims to help designers quantitatively assess potential problems early on, improving security and reducing design costs.
A method based on information-flow tracking uses gate-level logic to detect hardware Trojans that violate the confidentiality and integrity properties of third-party IP cores. Experiments on trust-HUB benchmarks show that the method reveals Trojan behavior and unintentional design vulnerabilities that functional testing cannot pinpoint.
Supply-chain traceability and electronics counterfeiting have become increasingly widespread issues for military and commercial electronics systems. In response to a DARPA SHIELD program directive, Northrop Grumman is leading a team to develop tiny, passive, near-field RFID chips, called dielets, which will be embedded in electronic component packaging. The design and implementation of dielets minimizes...
Computing device vendors can introduce malware that is nearly impossible to detect with known methods, but microservice solutions can limit the negative impact.
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