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The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.
In this work, we compare parasitic components between lateral nanowire-FET (LFET) and vertical nanowire-FET (VFET) based on ITRS 2015 using 3D Technology Computer-aided Design (TCAD). We compare the parasitic resistances and capacitances in accordance with channel thickness. Further, we analyzed the effects of parasitic components on device performance and proposed the direction of device scaling.
This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent Vth controllability. Low-temperature operation enables higher drive...
In this work, we conduct research on optimizing schemes for the RRAM-based implementation of CNN. Our main achievements contain: 1) A concrete CNN circuit and corresponding operation methods are developed. 2) Quantification methods for utilizing binary or multilevel RRAM as synapses are proposed, and our CNN performs with 98% accuracy on the MNIST dataset using multilevel RRAM and 97% accuracy using...
We report the single carrier transport properties in the p-doped/less-doped graphene nanoconstriction structures. In the doped graphene devices, the overlapped Coulomb diamond characteristics are observed around the charge neutrality point (CNF) at 5 K. Reducing doping in graphene by annealing, the periodic peaks appear in the certain gate voltage range around the CNP. Additionally, the non-overlapped...
Novel thin film transistor based on a graphene-ZnO Schottky junction has been demonstrated for display driver circuit applications. High transmittance over 80% in visible light wavelengths with a high on-off ratio over 104 are the merits of this device. All device fabrication processes completed at a temperature below 200°C will provide a unique advantage in the flexible display applications. The...
Monolayer graphene geometric diodes with neck width of 50 nm exhibit record high current asymmetry of 1.48. Diodes with neck angles of 30° and 45° show no significant change in asymmetry, while a reduction in asymmetry has been observed for a diode with a neck angle of 60°, attributed to the reduction in physical asymmetry of the diode structure.
The Fermi level of graphene in contact with the metal contact is a critically important factor for graphene-based device design. Fermi level pinning like behavior at the metal on a graphene can limit the contact resistance reduction and other device operations, especially in high workfunction metal cases. We report that this problem can be substantially alleviated by the hydrogen anneal at high pressure...
Inter-band tunneling in Si is a key mechanism for Esaki diodes and tunnel FETs. In nanoscale devices, the dopant states under high built-in electric field may significantly affect inter-band tunneling transport. Here, we introduce firsttime observations from measurements of nanoscale Si tunnel diodes of two main effects: (i) splitting of dopant minibands in high electric field, similarly to the Wannier-Stark...
In this work, the impacts of both nanowire diameter (Dnw) and Ge content (%) on the performance of Si1−xGex Gate-All-Around nanowire p-channel FETs (GAA pNWTs) are investigated. The variations in SiGe GAA pNWTs induced by Dnw variation, Ge content variation and some stochastic process variations including of random dopants fluctuation (RDF), gate edge roughness (GER), and metal gate granularity (MGG)...
In this paper, the dual-k spacer of nanowire-FET is investigated using a variety of materials compared with single spacer. The proposed structure shows significant improvement of delay characteristics and better electrostatic controllability than those of single spacer.
The quasi-ballistic hole transport capabilities of Ge and Si NWs were calculated using atomistic electron-phonon coupling and Boltzmann transport equation. Analyzing the forward and backward current fluxes, it was shown that the positive impact of high mobility of Ge is canceled by its slower energy relaxation, which results in comparable transmission coefficients and current transport capabilities...
Impact ionization [1,2], or electron-hole pair creation by charged particles, has been one of the central issues of semiconductor physics and devices. However, due to its complexity of the process, most experimental studies and their analyses have been macroscopic and phenomenological. This situation prevents us from exploring the fundamental physics of impact ionization and of high-energy charged...
This paper demonstrates and experimentally reports the highest ever performance boosting in strained silicon-nanowire homojunction TFETs with negative capacitance, provided by matched PZT capacitors. Outstanding enhancements of Ion, gm, and overdrive are analyzed and explained by most effective reduction of body factor, m < 1, especially for Vg>Vt, which greatly amplify the control on the surface...
Aiming at performance enhancements and robust reliability design of mono-layer transition-metal dichalcogenide (TMD) tunneling FET(TFET), W vacancy(Vw) defect is systematically studied in this work. Impacts of Vw defect's positions are characterized in WSe2 TTETs by using rigorous ab initio simulations. It is found that Vw defect that locates in the tunnel junction will increase Ion, while it has...
We have investigated dynamic characteristics of ferroelectric Hf02 (FE-Hf02) by considering multiple domain (MD) and linear domain-domain interaction. By using the calibrated MD model, experimental dynamic responses of FE-HfO2 can precisely reproduced, for the first time. Input voltage amplitude (Vin) and external resistance (R) dependences of dynamic responses in FE-Hfö2 revealed that dynamic term...
In this paper, a new modeling approach for understanding and designing a recently proposed steep subthreshold slope SOI transistor (i.e. PN-Body Tied SOI FET [1-3]) is proposed. We revealed that the abrupt switching operation can be modeled using a simple equivalent circuit comprising two cross-coupled voltage inverters (i.e. electron current and hole current inverters). The model will be useful for...
In this work, we have investigated the effect of thin SiO2 layer on switching variability of SiNx-based RRAM. We found that recessive LRS state generated in set operation results in large reset current and abrupt reset operation. The abrupt reset operation leads to large HRS distribution. To investigate the transient characteristics of switching process in detail, measurement environment is implemented...
Positive bias temperature instability (PBTI) of tunnel thin-film transistor (TFT) with poly-Si channel film is proposed for the first time. The novel interband tunneling transport mechanism of tunnel-TFT results in special PBTI behavior. For PBTI at 75 °C with stress voltage 10 V, tunnel-TFT exhibit excellent PBTI immunity compared to conventional TFT. However, the degradation of tunnel-TFT is getting...
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