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In this work, we studied the advanced nanofabrication technologies including electron beam lithography, blockcopolymer-based self assembly fabrication and their combination lithography, that is, directed self assembly (DSA). Nanostructures with a size of 10 nm order were successfully fabricated using these technologies. We attempted to further incorporate these nanostructures fabricated by these advanced...
In order to solve the repeated design of NoC router, this paper proposed a lightweight NoC router after a study of NoC's characteristics and Operating mode. In the low frequency data interaction application, the proposed router has a high cost performance. It can be mapped in a variety of NoC topology by changing the number of each internal module and that will help to reduce the design cycle of multi-core...
In near-threshold multi-voltage designs, large clock skew occurs between different voltage domains. Several works of power-mode-aware buffer (PMAB) were dedicated to diminish this clock skew. However, they were commonly based on circumstances that each power domain had at most two supply voltages. In this brief, we propose a multi-stage PMAB approach to diminish clock skew for multi-voltage multi-power-mode...
With the increasing demands of performance, yield, and turn-around time of smart device design, fast and accurate three-dimensional (3-D) numerical simulation has become indispensable and poses the computational challenge to the designers. On the other hand, the Monte Carlo (MC) method has the advantages of better parallelism, better scalability for very large structures, tunable accuracy, etc., and...
Model predictive control (MPC) based dynamic thermal management (DTM) is effective in managing temperature and power of multi-core systems at runtime. However, due to its centralized structure, such method has poor scalability. In this work, we propose a distributed MPC based DTM method, by dividing the full chip thermal model into submodels and decoupling the interactions among submodels with novel...
Coarse-Grained Reconfigurable Architectures (CGRA) can accelerate computing speed with high power efficiency. Based on its special architecture, a corresponding compiler is designed to map the applications onto CGRAs. In order to exploit its parallelism, we design an automatic parallelizer for the compiler. This tool is aimed to transform source code to target code with multiple sub-functions, which...
In this paper, an intelligent and low power EEG(electroencephalograph) processing multi-QOS(quality of service) DSP has been designed with the smicrf180nm technology used for EEG wearable Instrument. The bio-detection uses the Ag/Ag-Cl electrode sensor to extract the head skin's micro EEG signal, and uses the differential chopper-LNA circuit to cancel the 1/f, dc-offset voltage and other noises. On...
In order to mitigate the electric field crowdingingate dielectrics and solve the reliability issue, high dielectric constant (κ) materials such as Al2O3 was applied in SiC metal-oxide-semiconductor (MOS) capacitors. High quality thin film Al2O3 was deposited on 4H-SiC by thermal atomic layer deposition (ALD), followed by post deposition annealing (PDA). The PDA was conducted in oxygen atmosphere at...
We present a novel design of bulk transmit-receive (T/R) switch FET to reduce switch loss and harmonics. Along with this we present an improved low-noise amplifier (LNA) bipolar design in a 350nm SiGe BiCMOS technology for providing better WiFi RX path performance in 802.11ac wave-2 applications. Tighter lithography aspects of 180nm is utilized to make these critical performance advancements.
The power consumption in electronic devices is the major challenge as increasing the demand of IC chips. To lower the VDD and AC power (PAC), both high mobility material and steep turn-on device technology are useful. The ferroelectric high-κ HfZrO MOSFET can realize not only a small sub-threshold slope (SS) <60 mV/dec for low VDD and PAC, but also a smaller aspect ratio FinFET. The small bandgap...
Semi-custom design flow is an efficient way to design digital integrated circuit (IC). It realizes physical IC design through translating hardware description languages (HDL) into a GDS layout file. By running scripts, the HDL code is synthesized into a cell level schematic. Then, the placing and routing procedures are performed, violations are fixed, optimizations are achieved, and verifications...
The Ziggurat algorithm is an efficient way for building a Gaussian random number generator (GRNG), which is useful in many scientific and engineering applications. As the classic ziggurat-based GRNG includes nonlinear operations in judging the wedge and tail regions, which is complicated and resource consuming. An improved ziggurat algorithm is proposed by optimizing the accepting model with piecewise...
A quadrature voltage-controlled oscillator (QVCO) with low phase noise and low power consumption is proposed. In order to improve the oscillation frequency and reduced the phase noise, a feedback network composed of buffer amplifiers and capacitors is introduced to the QVCO. And a newly structured adjustable inductor is also used in QVCO, which can improve the tuning range without adding extra power...
Testing FPGA switching characteristics on general purpose electronic test equipment(GPETE) test platform has much lower financial cost and more accessibility than testing on Automatic Test Equipment(ATE). However, when testing on GPETE platform, test accuracy is more easily influenced by device under test(DUT) board and test equipment, and some kinds of stimuli such as maximum frequency stimulus is...
In this paper, a design of memory built-in self-test based on JTAG interface circuit applied in Power line communication chip is implemented with SMIC 0.18um CMOS 1P5M process. The memory built-in self-test circuit mainly includes JTAG interface and memory test circuits. Test data and test instruction can be sent and received through only 5 JTAG interface pins. It can also complete memory test with...
Context adaptive binary arithmetic coding (CABAC) is the entropy coding tool applied in the latest video coding standard, High Efficiency Video Coding (H.265/HEVC). CABAC achieves high coding efficiency but involves the bin-to-bin data dependency of Binary Arithmetic Encoder (BAE). This paper proposes a range updating structure with pre-bitwise-NOT (PBN) operation to shorten the critical paths in...
In order to make full use of the parallelism of NoC and improve the parallel communication ability between resource nodes, a high performance dual-port network and relative routing algorithm are introduced in this paper. Meanwhile, the Torus structure is also used in the design to further improve the network performance, which provides better connectivity of network and smaller radius. This paper...
This study presents a test scheduling strategy for multi-tower three dimensional (3D) stacked ICs (SICs). Towards the given complete stack, a session-less based test scheduling method is proposed. Experimental results show that the proposed method minimizes the total test time under the constraints of the number of test TSVs and test pins. Besides, it is found out that the 3D-SIC configuration in...
This paper presents a High-Voltage High-PSRR (HVHP) power management circuit used in high-precision battery parameters acquisition chip for Battery Management System for new energy vehicles. It consists of a pre-regulator, a high PSRR (power supply rejection ratio) self-regulated bandgap voltage reference (BGR), high voltage linear regulator, with the capability of soft start, over current detect,...
An improved power-rail electrostatic discharge (ESD) clamp circuit is presented in this paper. The proposed circuit maintains a much lower leakage current over the static-triggered circuit while the false-triggering immunity of the design is fairly superior to the traditional transient-triggered circuit. Besides, by utilizing the feedback technique and capacitance-boosting technique, the area occupied...
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