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This work investigates the static noise margin (SNM) of 6T SRAM composed of 2D semiconductor MOSFETs. A analytical current-voltage model for 2D semiconductor MOSFETs is applied to analyze all transistors in a 6T SRAM. Simulation model and method are built for basic 6T SRAM structure and that with S/D contact resistance. Effects on SNM of contact resistance and inefficient channel doping are studied,...
In graphene FETs, the work function (WF) of electrode materials has remarkable influence on contact properties of Metal/Graphene(M/G). MoOx is a material with extremely high WF, when inserting nanoscale MoOx(x<3) thin layer between the interface of source/drain electrode and graphene in graphene FETs, acting as an efficient hole injection layer, MoOx can induce p-doping to graphene and therefore...
Graphene is coupled with silicon quantum dots (Si QDs) on the top of bulk Si to form a hybrid photodetector. SiQDs cause the built-in potential of the graphene/Si Schottky junction to increase. Si QDs also significantly reduce the optical reflection of the photodetector. Both of the electrical and optical contributions of SiQDs enable the superior performance of the photodetector.
The scaling behavior of MOSFETs based on two-dimensional (2D) materials is investigated by means of numerical simulation and analytical modeling. Due to their ultimate thinness, 2D channel materials like MoS2 are perfectly suited to push the scaling limits beyond those of silicon. The electrostatic integrity of 2D transistors is governed by the chosen device architecture, substrate material, and gate...
This paper presents a novel hardening triple-well design for an six-transistors CMOS memory cell fabricated in 65 nm feature size. The new approach calculates the effects of single event transient (SET) with junction currents, which is derived based on device physics. Simulation presents that charge collection can be effectively mitigated with the use of guard ring contact in triple-well CMOS process...
Polarity modulation of single-layer WSe2 field effect transistor is investigated by using hydrazine as a solution-processable and effective n-type dopant for WSe2. Compared to the intrinsic hole-dominant ambipolar behaviors, highly effective n-type doping characteristics are achieved after hydrazine treatment. It is found that the on-current improves obviously by one order of magnitude and the metal-WSe2...
This paper presents an overview of three works about graphene-based resistive random access memory (RRAM). The fabrication, device performance and working mechanism of graphene-inserted electrode RRAM, RRAM based on laser-scribed reduced graphene and gate-controlled graphene-electrode RRAM are introduced. This work may inspire new design of high-performance RRAM based on two-dimensional material and...
In this paper, we optimized a heterojunction SOI-TFET with high-k dielectric overlap on SiGe-source region. Mole fraction (x) of the Si(x)Ge(1−x) has an important influence in the performance of the TFET. The optimized device has achieved 50.9mV/decades SS, which breaks the 60mV/decades SS barrier. It has realized 107 Ion/Ioff ratios and the OFF-state leakage current can be lowed to 10−14 A/µm level...
It is the first time, we propose a new reading mechanism for an ARAM-like 1T-DRAM by exploiting Punch-Through (PT) phenomenon. We simulated and investigated the results of a modified ARAM structure with respect to different channel length, channel thickness. We found that the structure has an acceptable programming window (33 µA/um) at shorter gate lengths. The retention time can be improved by using...
In this paper, we propose a capacitor-less 1T-DRAM structure with the pass-way trench for improving the Retention Time (RT). We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). The memory operation and its attractive performance in terms of programming window, retention time, and...
The emerging applications is the dominant factor that drives the evolvement of computer technologies and architectures. Among the emerging applications these days, neural networks are the most attention-grabbing one. To unleash the benefits of neural network, the architecture optimization is a necessity. In this paper, the architecture requirements of neural network is first reviewed. Then based on...
Single drain select transistor (DSL) in 3D Flash memory may exhibit higher leakage as compared with DSL in 2D NAND, because of worse subthreshold swing characteristics due to poly-Si channel. Select transistor leakage suppression is essential in 3D NAND Flash Memory, in consideration of boosting potential and program disturbance. Compared to single Si drain select transistor in 2D planner Flash Memory,...
In this paper, a n-type tunneling metal oxide field transistor with partial channel underlap (UTMOSFET) is proposed, which exhibits low subthreshold slope (SS). The proposed device is compared with typical TMOSFET. Using two dimensional device simulation tools Silvaco ATLAS, we exhibit the ID-VGS curves and energy band diagrams for both devices. Additionally, the influence of short channel effects...
In this study, the n-channel metal oxide semiconductor file effect transistor (MOSFET) with contact-etch-stop-layer (CESL) stressor, SiGe channel, and dummy poly gate is proposed. The simulated technique is utilized to explore the stress distribution of nMOSFET in the channel region induced by foregoing mechanical. The simulation results indicated the SiGe channel significantly affected the stress...
In this work, the photolithography processed nickel (Ni) grids were used to replace indium tin oxide (ITO) as the transparent anode for perovskite solar cells. The results show that the Ni grids have a senior adhesion ability to glass substrates than that of Ag grids, and the obtained device show a comparable short circuit current density (JSC) to that of ITO based device, while the open circuit voltage...
By the droplet-pinned crystallization method organic field-effect transistors with good device performance were fabricated based on ribbon-like TIPS-pentacene crystals. The electrical property of OFETs with ribbon-like TIPS-pentacene crystals developed by different concentration solutions is investigated. It is revealed that large and highly textured crystals tended to result in high mobility and...
An efficient approach to engineering the Al2O3/GaN positive interface fixed charges (Qit+) by post-dielectric annealing in nitrogen is demonstrated. The remarkable reduction of interface fixed charges from 1.44×1013 to 3×1012 cm−2 was observed, which leads to a record high threshold voltage (VTH) of +7.6 V obtained in the Al2O3/GaN MOSFETs. The positive interface charges were proposed originating...
Designing and fabrication of 4kV, 20A 4H-SiC PiN diodes with JTE junction termination structure have been investigated in this paper. A bevel mesa structure and a single-zone junction termination extension (JTE) have been employed to achieve the target voltage. Finally, an optimized mesa structure without sub-trench (mesa height of 2.2 µm and mesa angle of 20°) has been experimentally demonstrated...
Trapping effects still limit the application of GaN-based high-electron mobility transistors (HEMTs). This paper further characters traps in GaN HEMTs based on the drain current transients. A hybrid transient, which contains more valuable information of traps than the single trapping or detrapping transient was detected and analyzed. Three traps with different time constants were determined and their...
The threshold voltage variability of extremely narrow silicon nanowire channel FETs is intensively measured and statistically analyzed. The nanowire width is from 7nm down to 2nm. It is found that the Pelgrom coefficient of 7nm-wide nanowire FETs is much smaller than that of fully-depleted SOI FETs, while it rapidly increases as the nanowire width decreases down to 2nm. The increase in variability...
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