The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An ultra-low power frequency synthesizer based on a 28-nm CMOS dual-voltage controlled ring oscillator is presented. The technological dispersion and temperature effects are tackled thanks to a Delay locked loop (DLL) which sets a coarse tuning voltage. A back-gate fine tuning voltage is used to lock the oscillating signal on a pure reference with a Phase locked loop (PLL). The close-in intrinsically-poor...
This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm2. The silicon results demonstrate an excellent in-band phase noise of −90 dBc/Hz at 500 kHz offset with...
A compatible low-noise multi-phase voltage controlled oscillator is demonstrated in this paper. A compatible current steers are used to reduce the gain of VCO. The cascade structure of inverter is used to suppress the intrinsic noise and power supply noise. By increasing the output resistance of current steers with the cascade structure, the supply noise is suppressed. A modified inverter delay stage...
A quadrature voltage-controlled oscillator (QVCO) with low phase noise and low power consumption is proposed. In order to improve the oscillation frequency and reduced the phase noise, a feedback network composed of buffer amplifiers and capacitors is introduced to the QVCO. And a newly structured adjustable inductor is also used in QVCO, which can improve the tuning range without adding extra power...
This paper proposes a wideband ΔΣ fractional-N frequency synthesizer for software-defined radio application. The frequency synthesizer has two modes: the regular mode and the low-power mode. The regular mode and the low-power mode are selected to generate lower band frequency output for low-power applications and low band frequency signal with lower phase noise performance, respectively. The frequency...
A 12.5Gbps quarter rate SerDes CDR for high speed serial link communication is presented in this paper. The proposed dual loop structure consisting of frequency tracking loop and phase tracking loop has good input jitter rejection. A novel dual switching ppms lock detector is proposed to ensure proper switching of dual loops to prevent false locking. Moreover, a novel quarter rate bang-bang phase...
A quasi-closed-loop auto frequency calibration circuit for PLL with 180nm CMOS process is designed in this paper. The optimized structure could avoid the problem of start-up trap appearing in conventional closed-loop structure. The binary search method is adopted to reduce frequency sub-band searching time, which could accelerate the PLL locking process. The circuit is simulated by Spectre, and the...
This paper describes an inductorless phase-locked loop (PLL) for 12.8Gb/s (full rate) and 40Gb/s (quad-rate) serial link applications. An integer-N PLL with a very wide bandwidth is implemented in 65nm CMOS, working as a second part of a cascaded PLL system. A gain-boosted two-stage ring oscillator is designed to meet the speed and generate quadrature outputs. The measured tuning range of the proposed...
This paper proposed a wideband LC voltage-controlled oscillator (VCO) for FMCW frequency synthesizer with a large KVCO but small gain variation. An unequally biased varactor bank is used to ease gain variation problem, and a novel compensation circuit using a tunable negative-inductance cell is applied to further reduce gain variation over the whole tuning range without adjusting dead zones. Implemented...
In this Paper, a fractional-N frequency synthesizer fabricated in a 0.18µm process is designed for a FSK transceiver. The precision of the charge pump can be improved by exploiting the op amplifier. Based on capacitance multiplication technique, the area of loop filter is reduced. The fractional-N divider function is realized by the sigma delta modulator. FIR filter is designed in the input stage...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.