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The ion selectivity of nanochannel due to the wall surface charges is capable of inducing strong coupling between fluidic and ionic motion within the system, which has been overlooked in the study of nanofluidics. This interaction opens up the prospect of operating nanochannel as nanoscale devices for electrokinetic energy conversion. However, the very short channel lengths make the ionic movement...
A TiN/SiOx/Pt structure was fabricated at room temperature and its resistive switching behaviors were investigated. The device demonstrated a bipolar resistive switching behavior, good stability and excellent scalability. The size effect of resistance and the resistive memory behavior can be explained based on conducting filaments (CFs) composed of oxygen vacancies. The resistive switching behavior...
This paper presents a MTJ Based non-volatile SRAM in 45 nm technology. It combines fast and low power partners with time-division satisfaction of high performance and low leakage energy requirements. It can store and restore the data in memory cells, inputs, outputs, clock, and address signals. Simulations show that the maximum frequency can reach 4.5 GHz. When the sleep time is more than 105 seconds,...
In this paper, a source/drain design for vertical channel nanowire FETs involving extension doping profile, spacer dielectric constant and spacer width is proposed and demonstrated by TCAD simulation. The results show that asymmetric graded lightly doped drain (AGLDD) exhibits excellent SCE controllability and driving capability even with relatively large nanowire diameter. By adopting high-k spacer...
The formation of Ti/Al/Ni/Au ohmic contact in AlGaN/GaN high electron mobility transistor (HEMT) by microwave annealing (MWA) has been proposed and studied. In this paper, we investigated the electrical characteristics of this contact structure, as well as its transmission electron microscopy (TEM) images, to analyze the mechanism of MWA for the formation of ohmic contact. Our analysis indicates that...
We have proposed two algorithms to demonstrate the relationship between W oxidation time and switching speed in this paper. The demonstration is carried out on a 128Kb test macro of AlOx/WOx bi-layer RRAM which was fabricated with 0.18µm standard logic process. Increasing the W oxidation time properly could achieve a faster switching speed while the overmuch oxidation time will result in performance...
An improved 4H-SiC MOSFET has been presented with fewer static and dynamic losses. The novelty of the structure lies in a combination of a heavily doped n-type epitaxial layer on the drift layer (Current Spreading Layer, CSL) and a p-type implantation introduced in the middle of the JFET area (Central Implant Region, CIR). Heavily-doped CSL could significantly reduce the specific on-resistance by...
In this paper a novel Double-References and Dynamic-Tracking Writing (DR-DTW) scheme is proposed for Resistive Random Access Memory (ReRAM) to improve bit-yield due to tail-bit issues and high-temperature resistance variations. Based on this scheme a 128bit HfO2 ReRAM is implemented in UMC 0.13µm Mixed-Signal process. The test results show that the Ron/Roff window increases to 10×. Compared with transitional...
The effects of an intentional interface engineering of a heterogeneous CeO2-Nb:SrTiO3 interface on the resistive switching behaviors of HfO2-based resistive random access memory (RRAM) has been investigated. Switching parameters including set voltage, reset voltage, low resistance state and high resistance state, are greatly improved by the interface engineering. Besides, low power consumption RRAM,...
This paper presents device and mixed-mode simulations of single photon avalanche diode (SPAD) device. Device simulations show that the breakdown mechanism of our diode is indeed avalanche. Mixed-mode simulations can accurately simulate the ignition of the detector due to photon absorption, the fast avalanche current build-up, the self-sustaining charge-multiplication process, and the self-quenching...
SiC rectifier diodes are important components in the power electronics industry because they have advantages over conventional silicon diodes, including large currents, high operation temperatures, and other similar properties. In the devices' current-voltage characteristics, it is readily observable that the curves at different temperatures have a common cross-over point. We found that the temperature...
In this paper a SPICE model of bi-layer and bipolar metal oxide resistive random access memory (RRAM) is proposed. Stepped reset phenomenon in bipolar RRAM is included and the impact of buffer layer thickness on Ireset is reproduced. The model is verified by experimental results from AlOx/WOx based RRAM [1,2]. This model is useful for multi bits storage circuit design, read reference circuit design...
In this letter, an atomistic-level simulation model of bipolar TiO2 RRAM is addressed, which adopts the typical MIM structure and combines the equation of oxygen vacancy transport, current continuity and Joule heating. Based on the model, the dynamic formation and rupture of conductive filament are described in a 3D geometry model of COMSOL. Besides, the electro-thermal model with a conical shape...
Filament rupture/restoration induced by movement of defects, e.g. oxygen ions/vacancies, is considered as the switching mechanism in HfO2 RRAM. However, details of filament alteration during switching are still speculative, due to the limitations of existing experiment-based probing techniques, impeding its understanding. In this work, for the first time, an RTN-based defect tracking technique is...
The analysis of self-heating effect in a SOI LDMOS device under an ESD stress is presented in this paper. TCAD tools are used as the platform to explore the physical process of the bulk LDMOS device and the influence of buried oxide layer inserted in the substrate. Simulation results uncover that the buried oxide layer degrades the current-handling ability and changes the lattice temperature distribution...
A robust ESD device for 5V circuit protection was designed and fabricated in a 0.5-µm 5V CDMOS process. It is composed of multi-fingered GCNMOS and ballasting-resistor. The ESD performance of such device with strip layout style is investigated by employing transmission line pulse (TLP) measurement. A double-triggered phenomenon is detected in the multi-fingered GCNMOS with ballasting-resistor. And...
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