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This paper proposes the automatic design method of comparator circuit by combination of game tree search and partial optimization. Because game tree search can remove redundant calculation, simulation time can be reduced. Using partial optimization can confirm the convergence of the optimize function of HSPICE. Thus, the proposed automatic designed circuit can satisfy the required specific. Compared...
A systematic design methodology, composed of a BW/gain model and an offset modeling mechanism, is proposed for high-speed interpolation/averaging ADCs. The methodology is able to conduct a systematic analysis and reaches an optimized ADC design with given specs (i.e., resolution, speed, input range, power, input CM, etc.). It shows significant advantage over the traditional trial-and-error ADC design...
Low power design is critical in today's chip design. Clock tree takes much of chip power. “Clock tree cost” is introduced to help design low power clock tree. Five methods are proposed to reduce “clock tree cost” and improve clock tree efficiency. They include clock sink depth check, redundant scan mux check, redundant clock gating cell check, CCOPT (Clock Concurrent Optimization) and simple clock...
We present an efficient layout decomposition flow and the corresponding optimization algorithms to minimize the stitches for double patterning lithography. Also the given power/ground preprocessing method for the flow reduces the complexity, and improves the speed and quality to the layout decomposition. Experiments show that our algorithms can effectively get the better results compared with other...
In this paper, the power consumption of the integrated circuit is discussed. At first, take CMOS integrated circuit as an example, we analyze the source and composition of the power consumption of the integrated circuit and then, we elaborate on the optimization of the integrated circuit on system level, algorithm level and structure level, RTL level, gate level, transistor level, process level and...
The pre-bond through silicon via (TSV) probing tests and fault localization are important for yield assurance in 3D-SICs. This paper proposes an optimization algorithm to generate the preferable set of test sessions for pre-bond TSV probing tests. Test sessions generated by the optimization algorithm can not only get localization of faulty TSVs in TSV network, but also reduce test time and cost of...
Convolutional Neural Networks (CNN) is widely applied in modern machine learning and pattern recognition area. Not only performance, more and more attention is paid on energy efficient and scalable devices like FPGA as a better solution than CPU and GPU. In this paper, we propose methods to optimize CNN by fixed-point quantization, activation function approximation, loops and tasks pipelining and...
This paper describes a fast interconnect scheme and the optimized circuit for FPGA programmable interconnects to achieve great performance and static power reduction. The fast interconnect scheme including fast connection between logic blocks and optimization of wire segments are proposed to reduce path delay and increase connectivity. Furthermore, non-minimum channel length technology is applied...
In this paper, a new steep-slope device concept of resistive-gate field-effect transistor (RG-FET), which is operated by electrically induced abrupt resistance change of gate stacks, is discussed in detail and experimentally optimized. The fabricated RG-FET demonstrates both an ultra-steep subthreshold slope of below 5mV/dec over almost 2 decades of drain current and a high on-current competitive...
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