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We are facing many challenges for future nanoelectronic devices in the next two decades dealing with scaling, power consumption and computing performance. This paper presents the most promising solutions for the end of the roadmap in the More Moore and Beyond-CMOS fields, including innovative nanomaterials such as ultra-thin Si-Ge-III–V/OI, 2D layers (graphene, phosphorene, various transition-metal...
The electrical characteristics of Ti/p-SiGe contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. TiN was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/p-SiGe contact resistivity (ρc) increases, but its Schottky barrier height (SBH) decreases, which does not coincide with the regular ρc-SBH dependence. Using TiN/p-SiGe as a control sample,...
This paper presents compact modeling for multi-domain system-level simulation based on multi-physics that considers the energy conservation condition, in terms of respective potential and flow quantities. Models for both electrical and non-electrical domains are developed to design a flexible blood pumping system where the blood flow is driven by electrically control organic actuators. The electrical...
With bias conditions changed during irradiation, the bias dependence of the total dose radiation response of fully depleted (FD) silicon-on-insulator (SOI) n-channel MOS transistors (NMOSFETs) is investigated preliminarily. It is found that the threshold voltage shift of the FD SOI NMOSFETs as a function of total dose exhibits an abrupt inverse change, namely, a unexpected rapid reduction, with increasing...
0.18 µm narrow channel input/output (I/O) nMOSFETs with shallow trench isolation (STI) were exposed to 60Co γ-ray irradiation. The parameters such as gate current, transfer characteristics, output characteristics, conductance, transconductance, off-state leakage current, threshold voltage and sub-threshold slope are analyzed for pre- and post-irradiation. Test results show that the gate current, transfer...
This work investigates the static noise margin (SNM) of 6T SRAM composed of 2D semiconductor MOSFETs. A analytical current-voltage model for 2D semiconductor MOSFETs is applied to analyze all transistors in a 6T SRAM. Simulation model and method are built for basic 6T SRAM structure and that with S/D contact resistance. Effects on SNM of contact resistance and inefficient channel doping are studied,...
The scaling behavior of MOSFETs based on two-dimensional (2D) materials is investigated by means of numerical simulation and analytical modeling. Due to their ultimate thinness, 2D channel materials like MoS2 are perfectly suited to push the scaling limits beyond those of silicon. The electrostatic integrity of 2D transistors is governed by the chosen device architecture, substrate material, and gate...
This paper presents a novel hardening triple-well design for an six-transistors CMOS memory cell fabricated in 65 nm feature size. The new approach calculates the effects of single event transient (SET) with junction currents, which is derived based on device physics. Simulation presents that charge collection can be effectively mitigated with the use of guard ring contact in triple-well CMOS process...
In this paper, we optimized a heterojunction SOI-TFET with high-k dielectric overlap on SiGe-source region. Mole fraction (x) of the Si(x)Ge(1−x) has an important influence in the performance of the TFET. The optimized device has achieved 50.9mV/decades SS, which breaks the 60mV/decades SS barrier. It has realized 107 Ion/Ioff ratios and the OFF-state leakage current can be lowed to 10−14 A/µm level...
In this paper, a n-type tunneling metal oxide field transistor with partial channel underlap (UTMOSFET) is proposed, which exhibits low subthreshold slope (SS). The proposed device is compared with typical TMOSFET. Using two dimensional device simulation tools Silvaco ATLAS, we exhibit the ID-VGS curves and energy band diagrams for both devices. Additionally, the influence of short channel effects...
In this study, the n-channel metal oxide semiconductor file effect transistor (MOSFET) with contact-etch-stop-layer (CESL) stressor, SiGe channel, and dummy poly gate is proposed. The simulated technique is utilized to explore the stress distribution of nMOSFET in the channel region induced by foregoing mechanical. The simulation results indicated the SiGe channel significantly affected the stress...
An efficient approach to engineering the Al2O3/GaN positive interface fixed charges (Qit+) by post-dielectric annealing in nitrogen is demonstrated. The remarkable reduction of interface fixed charges from 1.44×1013 to 3×1012 cm−2 was observed, which leads to a record high threshold voltage (VTH) of +7.6 V obtained in the Al2O3/GaN MOSFETs. The positive interface charges were proposed originating...
This paper deals with a technique to reduce glitches in digital-to-analog converters (DACs) using Gray code input. These DACs are designed using MOSFETs, and their operation with glitch reduction was confirmed with SPICE simulation. It has been believed that good topologies of Gray code input DACs do not exist, but we show here their paradox. We also show with simulation that our Gray code input DACs...
A CMOS over-temperature protection(OTP) circuit working in sub-threshold region is proposed in this paper, which uses sub-threshold MOSFETs as a substitute for BJTs to sense the temperature, significantly reducing the quiescent current down to 5µA. It also improves the compatibility of the circuit, since it can be manufactured in standard CMOS process. The low voltage wide-swing cascode current mirror...
From the varying threshold voltage of MOSFET caused by the external factor, this paper analyzes the variation tendency of amplifier's gain. It makes clear how the gain of three different amplifiers changes in theoretical. After that, EDA tools are utilized to verify the theoretical calculation. The theoretical and simulation result show that threshold voltage(Vth) is a sensitive parameter of amplifier's...
An improved 4H-SiC MOSFET has been presented with fewer static and dynamic losses. The novelty of the structure lies in a combination of a heavily doped n-type epitaxial layer on the drift layer (Current Spreading Layer, CSL) and a p-type implantation introduced in the middle of the JFET area (Central Implant Region, CIR). Heavily-doped CSL could significantly reduce the specific on-resistance by...
This paper describes a complete process/design co-optimization methodology based on Fully Depleted SOI (FDSOI) technology. A process optimization is detailed through significant effective capacitance reduction, in order to optimize jointly frequency/leakage ratio and high frequency performances. In this objective, an efficient and low cost offset-spacers morphology has been designed to achieve maximum...
This paper presents a process, voltage, and temperature (PVT)-independent constant-gm bias circuit, designed in 0.18µm CMOS technology. In this paper, the conventional precise off-chip resistor is replaced by a MOSFET operating in triode region with a novel bias circuit, which behaves like a PVT-independent resistor. Simulations show that the maximum gm variation across process corners is ±5.2%, and...
The breakdown path which leads to the soft- and hard-breakdown in a MOSFET device can be identified from the experiment. It carries similar concept of the filament formation in RRAM device. Basically, RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path, i.e., from the leakage by measuring the transistor's Ig current as a function of time. In CMOS, these traps...
This paper investigates the reliability of junctionless MOSFETs based inverter by 3D TCAD simulation. The results show the I–V behavior of junctionless SOI-MOSFETs is highly resistant to accumulated fixed charge in oxide. Then the performance of junctionless device-based inverter is discussed. VM of juncitonless device-based inverter maintains within 0.05V and the transient response time shows very...
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