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A 2.4GHz Doherty power amplifier (DPA) using capacitance compensation is proposed in 0.18um TSMC process. Doherty configuration with self-biased cascode transistors is adopted to achieve high output power and efficiency in power back-off region. The lumped element π-network is employed to replace the quarter wave transmission lines and facilitates the integration. Placing the PMOS device in parallel...
This paper presents a directly triggered asynchronous successive approximation register (SAR) logic with variable delay unit. With the help of the designed logic, the CDAC can be settled directly by the comparator result that avoids long propagation delay as conventional SAR logic does. Moreover, a variable delay unit is designed which provides more settling time to the last several bits to get more...
A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by the active switch and merging the signal control circuit into trigger circuit of static power clamp. The proposed circuit is a whole-chip ESD protection scheme that has a low leakage and...
A layout technique via pulse quenching is tested in this paper. The limitation of layout technique is found by 3D device experiment. The new requirement of layout technique can be affirmed that layout technique via pulse quenching is more suitable in nMOS under 90nm technology.
The power consumption in electronic devices is the major challenge as increasing the demand of IC chips. To lower the VDD and AC power (PAC), both high mobility material and steep turn-on device technology are useful. The ferroelectric high-κ HfZrO MOSFET can realize not only a small sub-threshold slope (SS) <60 mV/dec for low VDD and PAC, but also a smaller aspect ratio FinFET. The small bandgap...
In this paper, the power consumption of the integrated circuit is discussed. At first, take CMOS integrated circuit as an example, we analyze the source and composition of the power consumption of the integrated circuit and then, we elaborate on the optimization of the integrated circuit on system level, algorithm level and structure level, RTL level, gate level, transistor level, process level and...
A LNTA with robust improvement of IIP3 over temperature and process is proposed. Four auxiliary transistors are employed to achieve 3rd nonlinearity compensation using DS (derivative superposition) method. In order to maintain the high IIP3 over process and temperature (PT) variation, transistor's nonlinearity under PT is explored and corresponding bias circuit is built to keep enhancement in IIP3...
In this paper, we first analyze an LNA core, cascode structure cut off frequency and power gain relationship with device parameters. Then we discuss the LNA design differences between FET LNA and SiGe LNA during design optimization. SOI floating body FETs have advantages in higher Ft in the optimized current biased region and can offer more design flexibility, while SiGe NPNs need much less trade...
A buck DC-DC converter with very high light load efficiency is presented in this paper. It introduces hysteretic control when the large output ripple problem is not critical, especially in light-load condition. Moreover, a fast-response zero current detector (ZCD) is adopted to make the converter work in discontinuous conduction mode (DCM). Due to hysteretic control extremely simplified the control...
In this paper, the radiation response of 90nm bulk Si MOS devices irradiated by heavy ions is experimentally studied. Due to the intrinsic random incident of heavy ions, different performance degradation is observed, such as threshold voltage shift, saturation current change and maximum transconductance degradation. These performance degradations may be attributed to the displacement damage in channel...
A novel digital logic circuit used in standard cell library is presented. In space application, the threshold voltage of NMOSFET will decrease, which influence the output characteristics of digital logic circuit seriously. With a new auxiliary circuit, the reliability and stability of digital logic gate circuit is improved. The structure configuration, circuit analysis and simulation result is compared...
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