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A 2.4GHz Doherty power amplifier (DPA) using capacitance compensation is proposed in 0.18um TSMC process. Doherty configuration with self-biased cascode transistors is adopted to achieve high output power and efficiency in power back-off region. The lumped element π-network is employed to replace the quarter wave transmission lines and facilitates the integration. Placing the PMOS device in parallel...
A 6th order Chebyshev active-RC complex filter for high linearity global navigation satellite (GNSS) receiver is proposed in this paper. The filter is synthesized from a 6th order leapfrog low pass filter where the frequency non-ideality compensation technique for integrator is used. High linearity demands a robust and stable IIP3 through the pass band. Meanwhile, the 35dB rejection spec at 1.5 times...
A wideband capacitor cross-coupled common-gate low-noise amplifier (CGLNA) featured with improved linearity is proposed. The linearity is enhanced by complementary multi-gated transistor (CMGTR) technique. The bulk voltage and scaling size are tuned to shift the nonlinear coefficients of auxiliary transistors, compensating the nonlinearity of main transistors. Simulated in a 0.18 µm RF CMOS process,...
Linear amplification with nonlinear components (LINC) is an attractive technique to achieve linearity amplification with high efficiency. The linearity and resolution of the delay line play a great important role for the performance of LINC transmitters. In order to overcome the limitation of linearity and resolution, a delay-based all-digital phase modulator with calibration algorithm is proposed...
A LNTA with robust improvement of IIP3 over temperature and process is proposed. Four auxiliary transistors are employed to achieve 3rd nonlinearity compensation using DS (derivative superposition) method. In order to maintain the high IIP3 over process and temperature (PT) variation, transistor's nonlinearity under PT is explored and corresponding bias circuit is built to keep enhancement in IIP3...
This paper presents that techniques of mathematics, such as number theory, statistics, coding theory, modulation, control theory, and signal processing algorithms besides transistor-level circuit design are required to enhance the performance of analog/mixed-signal circuit performance. Several research examples in the authors' laboratories are shown.
This paper presents a 24.25–26.65 GHz 6-bit phase shifter in 65nm CMOS technology. The proposed architecture of the phase shifter divides the 6-bit phase shifter into one 3-bit and three 1-bit sub phase shifters. The low resolution sub phase shifters can be implemented just by switches and sub VGA cells which can lower the phase error apparently. The phase shifter results in a simulated RMS phase...
The input buffer applied in the analog-to-digital converter (ADC) is to isolate the connection between the input signal and the sampling switch. In time-interleaved ADC structure for achieving high speed and high resolution, the distortion introduced by sampling circuit of sub-ADC channels affects the linearity of the input signal. A wide-band input buffer is proposed in this paper with 1.5GHz band-with...
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