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The sensitivities of a Monte Carlo simulation tool (PRESTAGE) to variation of input parameters are studied. When calculating the single event upset cross-section induced by proton direct ionization, PRESTAGE calculation results significantly change with changes in the sensitive volume and passivation layer thicknesses. When calculating cross-sections induced by proton indirect ionizations, PRESTAGE...
Reconfigurable solid state drive platform is necessary for the evaluation of emerging non-volatile memories. In this paper, we design a solid state drive prototyping system based on Xilinx Zynq chip, and further implement a ReRAM-based solid state drive system. ATTO Disk Benchmark is used to test the potential performance benefit of ReRAM-based storage. The superior random write performance demonstrates...
This work investigates the static noise margin (SNM) of 6T SRAM composed of 2D semiconductor MOSFETs. A analytical current-voltage model for 2D semiconductor MOSFETs is applied to analyze all transistors in a 6T SRAM. Simulation model and method are built for basic 6T SRAM structure and that with S/D contact resistance. Effects on SNM of contact resistance and inefficient channel doping are studied,...
This paper presents an overview of three works about graphene-based resistive random access memory (RRAM). The fabrication, device performance and working mechanism of graphene-inserted electrode RRAM, RRAM based on laser-scribed reduced graphene and gate-controlled graphene-electrode RRAM are introduced. This work may inspire new design of high-performance RRAM based on two-dimensional material and...
In this paper, we propose a capacitor-less 1T-DRAM structure with the pass-way trench for improving the Retention Time (RT). We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). The memory operation and its attractive performance in terms of programming window, retention time, and...
The emerging applications is the dominant factor that drives the evolvement of computer technologies and architectures. Among the emerging applications these days, neural networks are the most attention-grabbing one. To unleash the benefits of neural network, the architecture optimization is a necessity. In this paper, the architecture requirements of neural network is first reviewed. Then based on...
In this paper, an intelligent and low power EEG(electroencephalograph) processing multi-QOS(quality of service) DSP has been designed with the smicrf180nm technology used for EEG wearable Instrument. The bio-detection uses the Ag/Ag-Cl electrode sensor to extract the head skin's micro EEG signal, and uses the differential chopper-LNA circuit to cancel the 1/f, dc-offset voltage and other noises. On...
We have proposed two algorithms to demonstrate the relationship between W oxidation time and switching speed in this paper. The demonstration is carried out on a 128Kb test macro of AlOx/WOx bi-layer RRAM which was fabricated with 0.18µm standard logic process. Increasing the W oxidation time properly could achieve a faster switching speed while the overmuch oxidation time will result in performance...
Neutron radiation induced soft error rate (SER) of semiconductor devices is still an important issue. Both SOI FinFET and bulk FinFET are simulated to analyze the sensitivity to neutron radiation, including particle transport simulation, device simulation and circuit simulation. The results demonstrate that bulk FinFET can deposit more energy due to larger sensitive volume. And the peak value of current...
This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths...
We demonstrate SRAM circuit design techniques for enhancing performance, power and area (PPA) in 16 nm FinFET technology. The wordline overdrive (WLOD) assist circuitries with dual power rail are introduced for not only 6T single-port SRAM bitcell but also for 8T dual-port bitcell, improving minimum operating voltage (Vmin) by enhancing write-abilities. The read access times are also improved by WLOD...
Dielectric isolation of silicon on insulator (SOI) technology allows circuits to be designed that have reduced single event upset effects and are free from latch-up. For these reasons, SOI technologies are well suited for space applications. In this paper, we investigated both single event upset (SEU) and single event latch-up (SEL) effects of 512k bits SRAMs fabricated in SOI technology. The linear...
In this paper a novel Double-References and Dynamic-Tracking Writing (DR-DTW) scheme is proposed for Resistive Random Access Memory (ReRAM) to improve bit-yield due to tail-bit issues and high-temperature resistance variations. Based on this scheme a 128bit HfO2 ReRAM is implemented in UMC 0.13µm Mixed-Signal process. The test results show that the Ron/Roff window increases to 10×. Compared with transitional...
With the decrease of the transistor feature size, aging phenomena is becoming one key factor affecting the performance of the circuit. Digital measure the performance degradation is one of critical problems in aging adaptive design technique. In this paper, we propose a delay amplified digital (DAD) aging sensor circuit which is combined aging principle with delay amplified circuit. Firstly, a reference...
The effects of an intentional interface engineering of a heterogeneous CeO2-Nb:SrTiO3 interface on the resistive switching behaviors of HfO2-based resistive random access memory (RRAM) has been investigated. Switching parameters including set voltage, reset voltage, low resistance state and high resistance state, are greatly improved by the interface engineering. Besides, low power consumption RRAM,...
Significant change has occurred in the ESD and EOS testing of components and systems [1–7]. Evolutionary and revolutionary changes has occurred in the electronic industry in the area of testing of components and systems. In this paper, testing will be discussed in ESD, EOS, latch-up, and electromagnetic compatibility (EMC) and the evolution of new testing standards, test equipment, and testing methodologies.
A new current-mode sense amplifier is presented. It utilizes the positive feedback scheme to enhance stability and enlarge the voltage swing of bit-lines. Comparing with the referenced sense amplifier, the new structure could work in large scale circuits correctly and efficiently. And the average power consumption and area are reduced. Extensive simulations, based on 65-nm CMOS technology, have verified...
High Efficiency Video Coding (HEVC) is the latest video coding standard which aims to provide a much better coding performance than that of its predecessor, namely, H.264, especially for High-Definition (HD) videos. To fulfill such a goal, the Prediction Unit (PU) modes and partitions are more complex and the search range of Motion Estimation (ME) is much larger. As a result, ME becomes a bottleneck...
Memory that storages key or security code and other sensitive data may be subject to unauthorized access on a Network-on-Chip. In order to respond to this threat, network security storage solution based on chip RBAC security model is proposed. The security manager assigns the roles to the application operations which run on the NoC. Different roles have different access rights, and security manager...
An outdoor air quality monitoring system based on ZigBee wireless sensor network is presented in this paper. A wireless network is formed by coordinators, routers, terminal notes, and especially PPB (part per billion) level high precision sensors. Data, sampled and processed by terminal notes, are sent to routers or the coordinator through a serial port, then displayed on a screen of a PC. The concentration...
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