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This paper presents a MTJ Based non-volatile SRAM in 45 nm technology. It combines fast and low power partners with time-division satisfaction of high performance and low leakage energy requirements. It can store and restore the data in memory cells, inputs, outputs, clock, and address signals. Simulations show that the maximum frequency can reach 4.5 GHz. When the sleep time is more than 105 seconds,...
A quadrature voltage-controlled oscillator (QVCO) with low phase noise and low power consumption is proposed. In order to improve the oscillation frequency and reduced the phase noise, a feedback network composed of buffer amplifiers and capacitors is introduced to the QVCO. And a newly structured adjustable inductor is also used in QVCO, which can improve the tuning range without adding extra power...
Synchronous Switching Power Converters (SSPCs), which are suitable for fast-response high-efficiency applications, have become one of the research hot spots in recent years. A novel high-speed level shifter circuit with low power consumption is proposed in this paper, which is embedded in an integrated synchronous rectifier gate driver system. The proposed level shifter circuit consists of two parts:...
A novel self-turnoff control circuit for program process of one-time programmable (OTP) cell is proposed. Utilizing the current turnoff technology after the breakdown of OTP cell, it lowers the power consumption efficiently compared with traditional structures without turnoff mechanism. In addition, an additional delay circuit is also attached to the self-turnoff circuit to ensure the complete breakdown...
This paper proposes a wideband ΔΣ fractional-N frequency synthesizer for software-defined radio application. The frequency synthesizer has two modes: the regular mode and the low-power mode. The regular mode and the low-power mode are selected to generate lower band frequency output for low-power applications and low band frequency signal with lower phase noise performance, respectively. The frequency...
This paper presents a wireline communication receiver with merged continuous-time linear equalizer (CTLE) and decision feedback equalizer (DFE) summer circuit. The merged circuit removes the traditional CTLE and merge it into the following DFE summer to builds linear equalization so as to significantly reduce the receiver power consumption. Analysis for the conventional equalizer and proposed circuit...
A 12-bit 250MSPS Pipeline ADC with serial output interface is presented. The pseudo random (PN) calibration technique is used to improve the dynamic performance in the high speed ADC. A integrated serial output interface is implemented to convert 12 bit parallel data into a differential serial data stream. The whole pipeline ADC was fabricated in 180nm 1.8 V 1P5M CMOS process. Test results show that...
This paper presents a configurable 1/2/3 order Butterworth low pass(LP)/complex bandpass (CBP) filter for sub-GHz Applications in a 180-nm CMOS process. The filter employs operational transconductance amplifier (OTA) unit with feedforward capacitor instead of conventional two-stage amplifiers to broaden bandwidth while consuming no extra power. In order to achieve a good noise figure, extra noise...
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