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With aggressive scaling of silicon technology, integrated circuits (ICs) yield has emerged as a prominent concern. Yield loss comes from timing problems induced by process variations introduced by inaccuracy in nano-scale CMOS fabrication. To address this concern, we have developed a system to assist in optimizing yield and power. The system consists of timing violation sensors, clock duty-cycle controllers,...
A 32-channel ASIC has been designed and fabricated in a standard 0.35 μm CMOS technology for the read-out of Gas Electron Multiplier detectors to be used for beam monitoring in hadron therapy applications. Each analog channel is based on the classic CSA+shaper architecture, followed by a peak detector which works as an analog memory during the read-out phase. An analog multiplexer routes the outputs...
A SpV-resolution RFID ECoG data reader bas been designed and implemented in 65nm CMOS TSMC technology. The area occupancy is 1.8mm×l.9mm. In this paper, the design and measurement results are shown. The circuit average power consumption is less than 36μW for the analog part while the peak power of the digital one is 19mW (including the output buffers and protections) with supply of 1.2V, providing...
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