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This paper presents a method for adding several numbers represented in the Logarithmic Number System (LNS). The proposed technique is based on the normalization towards the largest input number. The distinct steps of the original two-input addition/subtraction using Fractional Normalization method (FN) [1] are modified in order to achieve performance and reduce hardware requirements. Three multi-operand...
An all-digital RF transmitter architecture capable of driving directly a switching RF power amplifier and therefore without the need of a high-speed RF DAC is presented. Modulation is achieved by directly modulating a direct digital synthesizer (DDS) generated signal. The proposed architecture is based on single-bit sigma-delta modulation using the introduced homodyne band-pass filter topology, which...
The class of 1-bit Multi-Step Look-Ahead (MSLA) ΣΔ modulators is presented. They take into account current and future quantization errors improving upon the stability and noise shaping characteristics of conventional 1-bit ΣΔ modulators. The MSLA modulator system is found to be equivalent to a number of parallel conventional ΣΔ modulators sharing a multi-input 1-bit quantizer. The number of look-ahead...
This paper is an extension of V-shape multi-scroll butterfly attractor in the fractional-order domain. The system complexity is increased by the new dynamics introduced by the fractional operator which make it more suitable for random signal generator. The effect of system parameters on controlling the attractor shape is investigated and compared with the integer order attractor. Maximum Lyapunov...
The next generations of vehicles are expected to support advanced services, such as object detection and recognition, risk identification and avoidance, car platooning, and others, which will require data transmission rates of the order of gigabits per driving hour. This unprecedented amount of data to be exchanged goes beyond the capabilities of existing communication technologies and calls for new...
The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i.e.: <1MHz). In order to extract the track information within the latency constraints (<5µs), a custom real-time system is necessary. We developed a prototype...
This paper proposes a novel population count circuit for Associative Memories (AM)s. Currently, AM chips requires a large number of silicon area for the population count circuitry. For this reason, is necessary an optimization in terms of area for the future AM devices to have a better memory density. A population count circuit counts how many blocks of the AM are in a matching state. If the count...
Free space optical (FSO) communication systems or point-to-point optical wireless communication links via light, have recently emerged as a very promising and commercially viable laser technology that comes up to the growing demands for larger available bandwidth, huge data rates and higher security level transmissions in a both energy-efficient and cost-effective manner. However, their performance...
This paper proposes a charge pump based on a charge controlled memcapacitor. The operation of the charge pump is investigated along with the mathematical analysis of the memcapacitor. Different implementations of charge pump are summarized. The proposed charge pump has the capability of driving low input voltage in range of 200mv and the capability of operating at the low frequencies which makes it...
Free-space optical communication systems are gaining popularity as a high-capacity, cost-effective and license-free wireless technology, addressing the bandwidth demands of existing and future wireless networks. The deployment scenarios of free pace optical links usually concern secure, fast and reliable connections. Thus, in this work, the performance of optical wireless communication systems is...
we present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available...
This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the one dimensional double humped logistic map as well as the two-dimensional delayed logistic map. Different analyses are introduced to measure the performance of the proposed...
In the cell placement problem a circuit's cells must be placed within a specified chip area so that they are row aligned and contain no overlaps. The problem is usually tackled in phases, whereby in the first phase a global placer performs an initial spreading of cells with regards to some optimization criterion, most commonly wire length minimization. The output of the first phase might violate alignment...
This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the double humped logistic map as well as the fractional order logistic map. The mixing of the map parameters and the initial conditions x0, offers a great variety for constructing...
Spark is one of the most widely used frameworks for data analytics. Spark allows fast development for several applications like machine learning, graph computations, etc. In this paper, we present Spynq: A framework for the efficient deployment of data analytics on embedded systems that are based on the heterogeneous MPSoC FPGA called Pynq. The mapping of Spark on Pynq allows that fast deployment...
An Organic Electrochemical Transistor model written in Verilog-A, a high level analog hardware description language, is presented. Using a polynomial approximation of the transistor DC characteristics, various phenomena in the operation of the device could be modeled. The error between experimental and simulated data was estimated very low for all cases of the simulated results. The model was imported...
This paper presents a generalized family of fractional-order oscillators based on single CFOA and RC network. Five RC networks are investigated with their general state matrix, and design equations. The general oscillation frequency, condition and the phase difference between the oscillatory outputs are introduced in terms of the fractional order parameters. They add extra degrees of freedom which...
Fifth generation (5G) wireless technology is a promising solution for multi-Gbps data rates in future mobile communications. The new devices are expected to operate at millimeter wave frequencies. To address the 5G requirements novel antennas have to be developed. In this paper the Teaching-Learning-Optimization (TLBO) algorithm is applied in order to design a dual-band E-shaped patch antenna. The...
In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of the main characteristics of the new chip are reduced power consumption and an increased memory cell area density by the use of two newly designed memory cell technologies. The aim of the new chip is to test the new technologies with realistic front-end functions. The integration of the AM...
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