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The Parallel Self Timed adder (PASTA) is based on a recursive formulation for performing multi bit binary addition. The operation is parallel for those bits and do not need any of the carry chain propagation. The main objective of this paper is to reduce the power consumption and also to increase the performance. The existing design attains good performance over random operand conditions without any...
In the present design algorithms, the speed of the multipliers is limited by the speed of the adders utilised. This work is dedicated for the design of a 16-bit multiplier which is proposed using a vedic sutra named Urdhva Tiryagbhyam from Vedic Mathematics. The 16-bit multiplier is realized using a 8-bit multiplier which inturn realized by a 4-bit multiplier and so on. Modified Ripple Carry Adders[7]...
Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In VLSI, low power dissipation is the main criterion in many electronic devices out of speed, area, etc., like mobile phones, laptops, high speed work stations etc., Due to the integration of many components on the VLSI circuit...
Addition is the most widely utilized arithmetic operations in any adder circuits. The performance of an adder is a speed determining factor for arithmetic operations. This project is proposed to analyse and compare the performance of various adder circuits in order to obtain the design of a high throughput aging-aware variable latency multiplier. The moderate performance degradation is achieved in...
As the size of MOS transistors are scaling down, energy dissipation has become a major consideration in nanometer CMOS circuits. In this paper, a Full-Adder is realized using XOR gate in sub-threshold region and the results shows that the device works perfectly without affecting its functionality keeping the power, delay and power-delay product at an optimum level. The analysis is done in Cadence...
A new charge pump boost converter is to solve the overflow output ripple problem of boost converter without losing the switching characteristics of the more efficiency of the converter. The modified efficiency improvement of charge-pump boost converter uses adaptive slope generator with hysteresis voltage comparison techniques, which has been fabricated with TSMC 180-nm CMOS technology processes....
A multiplier is the basic structural unit of many arithmetic logical units(ALU), digital signal processing(DSP) and communication system. So the area, speed and power consumption are the prime factors for the designing of multiplier circuits. QCA (Quantum dot-Cellular Automata) is one of the alternatives, which yields small size and low power consumption. In this paper, we proposed a 4-bit Vedic multiplier...
This paper presents architecture for a fused floating point three term adder unit. The fused or merge technique is described in this paper because in a fused technique three term addition is done in single unit. The purpose of doing this is to reduce delay, area as compared to traditional addition method. Several optimization techniques are used to reduce delay. The proposed design is implemented...
Now-a-days reducing the power consumption of the device is the most important factor in VLSI design. This paper deals with the low power, full voltage swing BCD addition using Gate Diffusion Input cell. The average power of proposed BCD adder is 10.2793 μWatt which is compared with the average power of conventional BCD adder and the average power of conventional BCD adder is 50.4721 μWatt. So the...
In this paper a work can be proposed in order to deliver that the Multiple constant Multiplication method is effective when we design an FIR Filter with direct form architecture with the possibility that it can become programmable transpose form Architecture and it configures into block FIR filter for the area and delay comprehension of many order FIR filters for both fixed and Rearranged the Blocks...
In this paper, a three operand floating point adder with reduced delay has been implemented. In this, the internal width which mainly gives the delay has been given compatible with IEEE Std-754. Here for designing three operand floating point adder, Realignment method, which avoid more than one sticky generation, an low cost OR-logic network in the replacement of comparer has been employed, to detect...
Multipliers are the important block in digital signal processing, high speed arithmetic logic and accumulate units. Because of the increasing limitations on delay, the importance of faster multiplication is getting increasing. For enhancing the speed of the multiplier design, many new techniques are being worked upon on the multiplier. The Vedic multiplier depends on the Urdhava-Tiryakbhyam sutra...
With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device...
High speed multiplier designs have been the primacy for multiplier dominated applications such as wireless communications, computer applications, and image processing. In this paper a high performance fixed word length multiplier design by using recently proposed technique to eliminate the error correcting word and a delay efficient parallel prefix Ling adder for final redundant binary to normal binary...
Ternary quantum logic plays a very important role for building high speed and efficient futuristic computers. It has several advantages over classical computing and binary quantum circuits. In this paper, the realization of basic ternary circuits for adder/subtractor, encoder and priority encoder are proposed and designed. These circuits are very essential for the construction of various computational...
This paper presents design of optimized high speed and low power Vedic multiplier based on Vedic sutra Urdhva Tiryagbhyam. Adiabatic logic is used to reduce the power consumption of Vedic multiplier and its performance is evaluated by comparing it with conventional MOS design. The power consumption of Adiabatic Vedic multiplier is less than power consumed by Vedic multiplier without adiabatic logic...
In this paper, Radix-4 Modified Booth Encoding (MBE) is used to generate partial product. The proposed 32-bit multiplier is based on pipelining. The main target is to reduce the delay of higher bits multiplier and speeding up the computation. The proposed design is implemented in Xilinx 14.2. The delay achieved is 2.826ns for computing 32×32 bit signed multiplication with maximum frequency of 353...
This paper presents a computational technique called “Vedic Mathematics” coupled with clock gating for designing a DSP co-processor that is fast as compared to other processors having conventional multiplier designs. A processor's speed is essentially determined by the speed of its multiplier and MAC blocks. In this paper we have designed a high-speed 16×16 bit multiplier. This architecture employs...
This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor...
Least mean square (LMS) algorithms are an important class of adaptive filters which are used in various real world applications because of its simplicity and efficient convergence performance. However the LMS filters have limitations in the designing like inner product computation which do not support pipelining type of applications. The adjustment of the critical path length is also a major drawback...
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