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This paper is based on cyclic redundancy check based encoding scheme. High throughput and high speed hardware for Golay code encoder and decoder could be useful in digital communication system. In this paper, a new algorithm has been proposed for CRC based encoding scheme, which devoid of any linear feedback shift registers (LFSR). In addition, efficient architectures have been proposed for both Golay...
Nowadays, the Leakage power is one of the major issue for CMOS circuit on nanometer technology. And it is increases as the process technology become finer and finer with device density increases. As the supply voltage lower down, gate oxide thickness have to reduce to reduce the threshold voltage which helps in maintaining the performance. But there is significant increase in leakage power dissipation...
In this paper, a two dimensional charge plasma based Single and hetero-gate dielectric Si0.5Ge0.5 doping-less tunnel field effect transistor (DL-TFET) is reported. Further, a comparative analysis of Si Single and hetero-gate dielectric DL-TFETs with Si0.5Ge0.5 Single and hetero-gate dielectric DL-TFETs are also presented for better understanding. The proposed Si0.5Ge0.5 DL-TFETs shows an improved...
The primary engine, powered the ascent of electronics is miniaturization. Presently Transceiver uses advanced CMOS technology and further miniaturization in the CMOS transistor is leading to unavoidable power dissipation. In this paper, we propose a double gate (DG) MOSFET based 5 GHZ Transceiver with Cascode low noise amplifier. The proposed Cascode Low noise amplifier is to reduce the power, overall...
Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In VLSI, low power dissipation is the main criterion in many electronic devices out of speed, area, etc., like mobile phones, laptops, high speed work stations etc., Due to the integration of many components on the VLSI circuit...
This paper presents a TCAD study on the performance of Si and Ge-GaAs hetrojunction dopingless tunnel field effect transistor (TFETs). Si tunnel device have low on current. So hetrojunction architecture is combined with dopingless structure for improving on current with smaller off current. Dopingless architecture uses low thermal budget for fabrication so hetrojunction dopingless TFET are suitable...
For photonic Digital processing All Optical Flip Flops are the major elements. External clock is the most important feature in Digital Signal Processing. All Optical JK Flip Flop is proposed and demonstrated in this paper. Based on the non linearity of Semiconductor Optical Amplifier (SOA) the principle of All Optical JK Flip Flop is designed. In this model we show a strategy of Optical pulse propagation...
As the size of MOS transistors are scaling down, energy dissipation has become a major consideration in nanometer CMOS circuits. In this paper, a Full-Adder is realized using XOR gate in sub-threshold region and the results shows that the device works perfectly without affecting its functionality keeping the power, delay and power-delay product at an optimum level. The analysis is done in Cadence...
In this paper, we present the enhanced performances of a compound Junctionless Double Gate MOSFET (JL DG-MOSFETs) using Indium Gallium Arsenide (InGaAs) as compound material and Aluminum Oxide (Al2O3) as oxide layer and compared with Silicon JL DG-MOSFET using SiO2 as an oxide layer. The proposed In0.53Ga0.47As-Al2O3 Junctionless DG-MOSFET provides a tremendous improvement in various factors like...
This paper presents a design of LC tank circuit using current mirror that achieves tuning range of 23.17% and Phase noise of −85dBc/Hz with a power consumption of 50uW for a power supply of 5V. The harmonics produced from VCO are extracted by using band pass filter (BPF) and amplified using common gate amplifier and cascode amplifier and differential buffer produces doubler output. The proposed design...
Digital designs makes use of Flip-flops (FFs) as the basic storage element. Pulse-triggered FF (P-FF), which is more popular than the master-slave based FF in high-speed applications consists of a single latch structure, hence Explicit type pulse trigger generator with pulse width control with performance optimization in power, delay, and area, design space exploration is important, In Explicit, one...
As technology enters into deep submicron regime, subthreshold leakage power increases exponentially and become a limiting factor in the performance of portable and battery operated electronic devices. To increase the life of battery and computational capacities of portable devices the reduction of power in standby/ sleep mode is evident. Now a day's power dissipation emerged as a major design constraint...
This paper discusses the effect of RE-GAA FinFET parameter on short channel characteristic. The Fin height, width and gate oxide thickness are varied and its effect on short channel characteristics like Ion, Ioff, DIBL, sub-threshold swing are observed. The simulated results demonstrate the dependency of DIBL on Fin thickness instead of Fin height. The increase in the height of the Fin results in...
A multiplier is the basic structural unit of many arithmetic logical units(ALU), digital signal processing(DSP) and communication system. So the area, speed and power consumption are the prime factors for the designing of multiplier circuits. QCA (Quantum dot-Cellular Automata) is one of the alternatives, which yields small size and low power consumption. In this paper, we proposed a 4-bit Vedic multiplier...
Now-a-days reducing the power consumption of the device is the most important factor in VLSI design. This paper deals with the low power, full voltage swing BCD addition using Gate Diffusion Input cell. The average power of proposed BCD adder is 10.2793 μWatt which is compared with the average power of conventional BCD adder and the average power of conventional BCD adder is 50.4721 μWatt. So the...
This paper represents the energy efficient ultra low power adiabatic sequential logic circuits in sub-threshold regime for the first time in literature. Here, Efficient Charge Recovery Logic (ECRL) based on Differential Cascode Voltage Swing (DCVS) is adopted for the implementation of the circuits to achieve the ultra low power dissipation in sub-threshold regime. Single sinusoidal source is used...
In the field of industrial application self checking designs have been playing a vital role as they appear to be providing high fault coverage with less risk. A Fin FET based self checking XOR/XNOR circuit is introduced that provide fault secure and self-testing applications. The design since proposed is simulated using Cadence spectre FinFET 20nm technology at various supply voltages associating...
In this paper, we have proposed thermal and threshold voltage analysis of GaN MOSFET with AlGaN/GaN heterostructure for high power and high frequency applications. The extremely high 2 Dimensional Electron Gas density (2DEG) helps to carry more output current. Normally off behaviour of the device is obtained by the replacement of AlGaN barrier layer with gate insulator, which helps to reduce the power...
Power consumption in test becomes a higher barrier for consideration in test of any combinational circuit is high during test mode as in its normal mode of functioning as enormous power dissipation seriously affects the chip reliability. Many techniques are proposed to lower down the test power. In scan based design, rippling transition created by test patterns shifting along the scan chain not only...
With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device...
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