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We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows...
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