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In parallel to presentations documenting the performance of state-of-the-art FDSOI CMOS devices, we discuss selected physical mechanisms and emerging device architectures enabled by FDSOI technology.
This paper presents an ultra thin body Si n-TFET which exploits a multi-finger gate layout and steep junction formed by dopant implantation into silicide (IIS) process. The sub-threshold slope (SS) reaches a minimum value of about 45 mV/dec, average SS of <60mV/dec and 71mV/dec over one and three decades of drain current, respectively. A remarkable high Ion/Ioff ratio (∼109) is achieved due to...
Low voltage transistors are being developed to achieve steep, less than 60 mV/decade, subthreshold swings at room temperature. This paper outlines progress, technical challenges, and applications for these devices.
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