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We demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options...
FDSOI technologies are very promising candidates for future CMOS circuits as they feature low variability, improved short channel effect and good transport characteristics. In this paper, we review the main electrical techniques and methodologies used to characterize the important MOS device parameters. First, the capacitance-voltage measurements are considered for the vertical stack characterization...
In this paper, we study the impact of material parameters (i.e. effective mass and bandgap) for two-dimensional (2D) material based tunneling FETs (TFETs) on circuit level metrics. We estimate circuit level metrics (i.e delay and energy consumption) of 2D TFETs at different target OFF current (IOFF) for various combination of material parameters. To fulfill a given IOFF requirement for circuit level...
We present a simulation study addressing the physics and design of ferroelectric MOSFETs and, in particular, we argue that a retrograde channel doping profile may help obtain a subthreshold swing well below 60mV/dec. Our analysis suggests that ferroelectric MOSFETs should be operated at gate voltages smaller than those triggering the hysteretic behavior, and have the potential to realize on current...
We have developed a physics based model for negative capacitance (NC) FinFETs by coupling the Landau-Khalatnikov model of ferroelctric materials with the standard BSIM-CMG model of FinFET. We apply our model to thin film Y-HfO2 (yttrium-doped hafnium oxide) based NC-FinFETs designed using state of the art 22nm technology node FinFETs. Using the same ferroelectric material, we demonstrate a device...
This paper presents the fabrication, electrical characterization, and simulation of planar single electron transistors. Two single electron transistors facing each other have been used to demonstrate single charge detection. The manufacturable fabrication process combined with both single charge detection and the simulation tool are a powerful platform for quantum cellular automata that can be applied...
Low voltage transistors are being developed to achieve steep, less than 60 mV/decade, subthreshold swings at room temperature. This paper outlines progress, technical challenges, and applications for these devices.
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