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With drastic device shrinking, low operating voltages, increasing complexities, and high speed operations, radiation-induced soft errors have posed an ever increasing reliability challenge to both combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise efficient soft error rate (SER) estimation methods, in order to evaluate the soft error vulnerabilities...
Modern embedded system must efficiently exploit parallelism at thread-and instruction-level to achieve the best performance with the lowest energy consumption possible. While Multiprocessor System-on-Chip (MPSoCs) are a commonly used solution, they do not provide an effective environment for software production, as each processing element implements a different Instruction Set Architecture (ISA)....
This paper presents a method to use floating gate (flash) transistors to implement low power ternary-valued digital circuits targeting handheld and IoT devices. Since the threshold voltage of flash devices can be modified at a fine granularity during programming, our approach has several advantages. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed...
This paper proposes a dual-clock based solution for QC-LDPC partially parallel flooded decoders. It aims at reducing memory and routing overhead, while maintaining a high degree of parallelism at processing node level. We take advantage of the high memory working frequencies with respect to the processing units, and use two clock domains: a high frequency for memory and the barrel shifter based routing...
Approximate Computing is revealing a new design paradigm which trades algorithms precision off for enhancing performance parameters, commonly energy consumption and computation time. Applications which are characterized by the inherent resiliency property tolerate some quality loss, w. r. t. the optimal result. The approximation is accomplished by combining substitutions of fully-precise block operations...
This work presents a comparative analysis of Si/Ge and GaSb/InAs heterojunction Tunnel FET (TFET)-based cellular neural networks (CNNs). TFET-based CNNs are also compared against an equivalent FinFET-based CNN. A simulation methodology is shown to project realistic estimation of TFET-CNN performance based on the measured IDS-VGS characteristics of TFETs. III-V-TFET (i.e., GaSb/InAs TFET) shows a higher...
Convolutional neural network (CNN), well-knownto be computationally intensive, is a fundamental algorithmicbuilding block in many computer vision and artificial intelligenceapplications that follow the deep learning principle. This workpresents a novel stochastic-based and scalable hardware architectureand circuit design that computes a convolutional neuralnetwork with FPGA. The key idea is to implement...
This paper proposes a method to explore the design space of FinFETs with double fin heights. Our study shows that if one fin height is sufficiently larger than the other and the greatest common divisor of their equivalent transistor widths is small, the fin height pair will incur less width quantization effect and lead to better area efficiency. We design a standard cell library based on this technology...
Most prior work on hardware reliability make use of module (spatial) redundancy or time redundancy. In the first case, these methods assume that each module is exactly the same. Multiple module replicas implementing the same logic function are executed in different hardware channels and a voting scheme detects if the outputs match or not. In the second case, they re-compute the result using the same...
Due to the increasing proliferation of computing systems in diverse application domains, the need for application-specific design of multicore/manycore processing platforms is paramount. In order to tailor processors for application-specific requirements, a multitude of processor design parameters need to be tuned accordingly. Tuning of processor design parameters involves rigorous and extensive design...
Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However,...
Important characteristic of any VLSI circuit isits power consumption, reliability, operating speed and siliconarea. Dynamic CMOS designs provide high operating speedscompared to static CMOS designs combined with low siliconarea requirements. Pipelines can be used for achieving highcircuit operating speeds. However, as the operating frequencyincreases, the number of pipeline stages should also increaseand...
This paper describes a procedure that computes a compact set of seeds for LFSR-based test generation using a fully-specified compact test set. The test set provides a target number of seeds that is not constrained by the LFSR. The procedure uses two techniques to produce a compact set of seeds. (1) It attempts to match a seed to a test in the compact test set, but without requiring a perfect match...
In this paper, a low power 5-bit hybrid flasharchitecture is proposed. The proposed analog-to-digital con-verter (ADC) uses appropriate combination of both conventionaldouble-tail comparators and standard cell comparators. Stan-dard cell comparators are used to reduce power consumption. Thus, the proposed hybrid architecture results in extendeddynamic range when compared to standard cell and thresholdinverter...
On-chip voltage regulation using distributed Digital Low Drop Out (LDO) voltage regulators has been identified as a promising technique for efficient power-management for emerging multi-core processors. Digital LDOs (DLDO) can offer low voltage operation, faster transient response, and higher current efficiency. Response time as well as output voltage ripple can be reduced by increasing the speed...
Power gating (PG) is an effective power efficiency improvement technique. Future general-purpose graphics processing units (GPGPUs) will likely feature hundreds of compute units (CUs) and be power constrained, which leads to serious challenges to existing PG methodologies. In this paper, we propose novel design-time and run-time techniques to effectively implement power gating in future GPGPUs. Based...
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