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This paper presents a post-placement technique for through-silicon-via (TSV) induced thermal mechanical stress reduction. Thermal mechanical stress causes several critical failures such as material fracture (interfacial delamination and silicon substrate cracking) and TSV stress migration (SM). The von Mises stress is used as a material fracture metric. An analytical TSV SM model is used, which replaces...
Electrostatic discharge (ESD) is a well-known problemin integrated circuits that affects its reliability, yield and cost. It is important to design ESD protection circuits that are ableto prevent ESD related yield loss [1]. In this work, a 65 nmstatic clamp with a thyristor as a delay element to extend the ontime of the clamp during the ESD event is presented. Simulationand measurement results show...
Physical unclonable functions (PUFs) provide a fast and cheap solution to secret key generation. Natural variations in silicon create unique "fingerprints" that are useful for identification. In a 6T SRAM array, these variations cause individual cells to skew their power-on tendency toward storing a 0 or a 1. Wearout effects interfere with those variations, changing the power-on...
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