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Physical Unclonable Functions (PUFs) use random physical variations to map input challenges to output responses in a way that is unique to each chip. PUFs are promising low cost security primitives but unreliability of outputs limits the practical applications of PUFs. This work addresses two causes of unreliability: environmental noise and device aging. To improve reliability, we constructively apply...
The emerging field of neuromorphic computing is offering a possible pathway for approaching the brain's computing performance and energy efficiency for cognitive applications such as pattern recognition, speech understanding, natural language processing etc. In spiking neural networks (SNNs), information is encoded as sparsely distributed spike trains, enabling learning through the spike-timing dependent...
Presently, almost all timing analyses and optimization tools are based on the strategy of setup and hold time constrained flip-flop timing model. However, this is a big mismatch with the timing characteristic of the real life flip-flops, which is so called flexible flip-flop timing, in which the clock-to-Q delay of every flip-flop may vary dynamically according to its setup and hold skews. This work...
With drastic device shrinking, low operating voltages, increasing complexities, and high speed operations, radiation-induced soft errors have posed an ever increasing reliability challenge to both combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise efficient soft error rate (SER) estimation methods, in order to evaluate the soft error vulnerabilities...
This paper describes a procedure that computes a compact set of seeds for LFSR-based test generation using a fully-specified compact test set. The test set provides a target number of seeds that is not constrained by the LFSR. The procedure uses two techniques to produce a compact set of seeds. (1) It attempts to match a seed to a test in the compact test set, but without requiring a perfect match...
Matrix-vector multiplication, as a key computing operation, has been largely adopted in applications and hence greatly affects the execution efficiency. A common technique to enhance the performance of matrix-vector multiplication is increasing execution parallelism, which results in higher design cost. In recent years, new devices and structures have been widely investigated as alternative solutions...
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