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A MANET consist of a collection of wireless mobile nodes in which packets are transmitted from one to another node via intermediate nodes within range. To find an efficient routing protocol, which is used to transmit data from source to destination across whole network, is a major issue in networking research. MANETs are flexibly distributed that can change their locations and are self-configurable...
Heterogeneous Network consists of wired and wireless network. In these networks, congestion control and quality of service is major issue. Due to this issues, delay and jitter are increased which decreases the performance of network. For reducing this issues there are various queue management techniques which are classified as Active Queue Management and Passive Queue Management. AQM consists of access...
A mobile ad hoc network (MANET) is a collection of wireless mobile nodes that can communicate without any centralized administration or fixed infrastructure. Because of limited wireless link capabilities, nodes with heavy traffic will reduce their energy rapidly and increases the possibility of congestion and path disconnection. Hence, load balancing and congestion is necessary in MANET. Thus, this...
The efficiency of a router in a Network on Chip (NoC) is characterised by good performance, minimum packet latency, area and power. In this paper, we propose an adaptive deflection router for mesh NoC which offers higher speed of operation by reducing the router critical path latency. We propose a single cycle router that uses an intelligent decision making logic to store deflected flits in minimum...
The multiply and Accumulate unit consists of a multiplier unit for multiplication and the product of multiplier is added up with previous result by using an adder. The result of a MAC unit is stored in an Accumulator. MAC is one of the part of digital processing systems. By reducing the delay of multiplier and adder, the overall delay of MAC unit can be reduced. In this paper the MAC unit is designed...
Memory is an important part of any digital circuit in which data is stored and retrieved. Technology scaling, lower operating voltages and high integration densities leads for failures in the reliability of memories. The main problem is Single Event Upsets (SEUs) that alters the memories from its normal way of functioning. This paper presents design and implementation of Majority Logic (ML) detecting/decoding...
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