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In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10−15 A/µm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the...
Retention characteristics of a 3-D NAND flash cell with tube-type poly-Si body are investigated at a high temperature (T) depending on program (P), neutral (N), and erase (E) states of adjacent cells. The trap density (Nt) in the nitride storage layer of the cell is extracted by utilizing retention model and deriving related equations in cylindrical coordinate. By programming or erasing adjacent cells,...
Brain-inspired non-Boolean computing paradigms are gaining wide interest due to their error resilient nature and massive parallelism. This work explores oxide-based compact oscillators for oscillatory neural networks (ONN). We demonstrate for the first time, best in class high-frequency performance at 500 MHz and low power (< 200 µW). The superior figures of merit are achieved due to device engineering...
We demonstrate a cost effective 65-nm SOTB CMOS technology for ultra-low leakage applications. Novel single p+poly-Si/Hf/SiON gate stack of mid-gap work function and precise GIDL control achieved ultra-low leakage of 0.2 pA/µm, which corresponds to approx. 100nA/chip (100k gate logic). Now the SOTB technology can provide three options from ultra-low voltage to ultra-low leakage that covers a wide...
We report the world's smallest field effect transistors (FETs) with channel lengths of 32 nm including c-axis aligned crystalline (CAAC) In-Ga-Zn-O as their active layers, which achieve low off-state leakage currents. Furthermore, these FETs exhibit excellent subthreshold swing values despite having thick gate insulating film. The FET operation has been achieved owing to the 3D gate structure with...
We have fabricated high-performance self-aligned top-gate InGaZnO TFTs with novel silicon-like source and drain (S/D) parasitic resistance (RSD) reduction processes. Ar ion implantation (Ar I/I) formed S/D extension layers and reduced RSD by inducing high-density carriers. First demonstration of self-aligned S/D metallization processes on InGaZnO surface (In-Ti alloy formation), just like silicidation,...
A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (LG) around 22 nm, an improvement which is predicted by modeling...
A novel damage recovery scheme using the oxygen showering post-treatment (OSP) is proposed to recover patterning damages and to improve electric and magnetic properties of p-MTJs, and its array yield. By applying our OSP to 25nm p-MTJs cell array, the MR was increased from 99% to 116% and the Isw was decreased from 41.1uA to 28.7uA. Moreover, electric short fails of MTJs array due to metallic by-products...
We have developed a perpendicular-anisotropy magnetic tunnel junction (p-MTJ) stack with CoFeB free layer and Co/Pt multilayer based synthetic ferrimagnetic (SyF) pinned layer that withstand annealing at a temperature up to 420°C (that compatible with CMOS BEOL process) by controlling boron diffusion. We demonstrated the 10 nmφ p-MTJ with double CoFeB/MgO interface tolerable against 400°C annealing...
High voltage I/O FinFET device optimization for a 16nm system-on-a-chip (SoC) technology is presented. After careful optimization through high electric field (E-field) mitigation by junction engineering, I/O FinFET devices with leakage current reduction by 1∼2 orders, hot carrier injection (HCI) lifetime improvement by 2.8×/1.2× for N- and PMOS, respectively, and junction breakdown voltage (Vbd) improvement...
We present a state-of-the-art fabrication technology and physics-based model for molybdenum disulfide (MoS2) field effect transistors (FETs) to realize large-scale circuits. Uniform and large area chemical vapor deposition (CVD) growth of monolayer MoS2 was achieved by using perylene-3,4,9, 10-tetracarboxylic acid tetrapotassium salt (PTAS) seeding. Then, a gate first process results in enhancement...
A performance upgrade of our 14nm FDSOI technology is reported in this paper. Compared to our previous 14nm FDSOI assessment, a −17% delay at the same leakage is demonstrated. We show that the AC performance of 28nm FDSOI at a 0.9V supply voltage is reached at 0.6V in 14nm FDSOI technology. This corresponds to a 50% increase in frequency at the same dynamic power, or a 65% power saving at the same...
This paper presents an AM receiver implemented in a flexible a-IGZO TFT technology. The circuit consists of a four-stage cascode amplifier at the RF input, a detector based on a source follower, and a common source circuit for the baseband amplification. The measured conversion gain is very flat and exceeds 15 dB from 2 to 20 MHz carrier frequency range, which covers a relevant portion of the shortwave...
This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4µm2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a...
We demonstrate a process flow for creating gate-all-around (GAA) Si nanowire (SiNW) MOSFETs with minimal deviation from conventional replacement metal gate (RMG) finFET technology as used in high-volume manufacturing. Using this technique, we demonstrate the highest DC performance shown for GAA SiNW MOSFETs at sub-100 nm gate pitch, and functional high-speed ring oscillators.
We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We show that the performance of these devices is substantially improved by high-pressure (HP) deuterium (D2) anneal, which is ascribed to a 2x reduction in interface trap density (DIT). Furthermore, it is found that (1) TMAH treatment of SiGe prior...
This paper presents a system consisting of an array of thin-film microphone channels on glass, which can be formed on large substrates. Each microphone channel consists of a polyvinylidene difluoride (PVDF) piezoelectric transducer as well as amplifier and scan circuits based on amorphous-silicon (a-Si) thin-film transistors (TFTs). The scan circuits multiplex signals from multiple channels to a CMOS...
Adding functionality to a passive Si interposer used in 2.5/3D integration, can result in system cost reductions. In this work, active components (diodes, BJT, …) have been integrated on Si interposer using a new low-mask process flow. This low-cost process enables: (1) to move part of the area hungry ESD protection from the stacked dies to the interposer; (2) the realization of pre-bond testable...
Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.
For the first time, AC lifetime in Si-cap/Ge and GeO2/Ge pMOSFETs is investigated and it must not be predicted by the conventional DC stress method with a measurement delay. This is because the energy alternating defects are generated in Ge devices but not in Si, which introduces additional generation under DC stress.
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