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This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently...
This study proposes a 7T1R nonvolatile SRAM (nvSRAM) to 1) reduce store energy by using a single NVM device, 2) suppress DC-short current during restore operations through the use of a pulsed-overwrite (POW) scheme, and 3) achieves high restore yield by using a differentially supplied initialization (DSI) scheme. This initialization-and-overwrite (IOW) 7T1R nvSRAM improves breakeven-time (BET) by...
We have shown a practical device design guideline for sub-0.2V ultra-low power, steep slope ferroelectric FET using negative capacitance (NC) focusing on operation speed, material requirement, and energy efficiency for the first time. The operation speed is determined by finite switching time of ferroelectric polarization. For low supply voltage and hysteresis-free design, there exists a ferroelectric...
A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (LG) around 22 nm, an improvement which is predicted by modeling...
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