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We introduce for the first time a novel integration scheme of CBRAM cells, where the Cu electrode is patterned using a subtractive dry-etching process. We demonstrate excellent performances of 30nm-size cells (1µs-write at ≤50µA, >106 endurance, excellent retention at 150°C) as well as scaling potential of CBRAM down to 10nm-node using 5nm-thick Cu electrodes.
We present a novel selector made of doped-chalcogenide material. This selector not only achieves low holding voltage (0.2 V) and large on/off ratio (>107), but also exhibits the high on-current density (>1.6 MA/cm2) and large hysteresis window (1.2 V). Besides, excellent selector performances with ultra-low off-state leakage current (10 pA), high switching speed (<10 ns), high endurance (>10...
A new phase change material that provides fast SET speed, high cycling endurance, and large resistance window suitable for MLC SCM is investigated. Thorough understanding of the factors that affect the resistance distribution taught us to avoid operating near the melting temperature of the phase change material. By exploiting the self-converging property of low current SET operation we have designed...
For the first time, we present a Phase Change Memory (PCM) device with an optimized Ge-rich GeSbTe (GST) alloy integrated on a 12Mb test vehicle. We confirm that PCM can guarantee high data retention in extended temperature range and we provide the understanding of the high thermal stability of the two programmed states. We show how the elemental distribution reaches an equilibrium at the core of...
Multi-level-cell (MLC) is a critical technology to achieve low bit cost for phase change memory. However, resistance drift is an intrinsic material property that kills memory window and imposes formidable challenges for MLC. In this work, we report a radically different sensing concept that exploits the non-linear R-V characteristics of PCM that can easily accommodate 8 resistance levels in three...
We demonstrated that reduced graphene oxide (rGO) can suppress electromigration (EM) of Cu interconnect lines. This improvement in the EM lifetime is attributed to the presence of functional groups between the rGO and Cu atoms. Further enhancement of the EM lifetime was achieved by increasing the functionality of graphene by mixing graphene oxide (GO) with polyvinylpyrrolidone (PVP). It is revealed...
A high-programming-throughput three-dimensional (3D) vertical chain-cell-type phase-change memory (VCCPCM) array for a next-generation storage device was fabricated. To increase the number of write cells at one time by reducing resistance of bit and source lines, the VCCPCM array includes plate electrodes and double-gate vertical-chain-selection MOSs with 5-nm-thick poly-Si channels. In addition,...
A 50nm topological-switching random-access memory (TRAM) was fabricated for the first time. A high-quality GexTe1−x/Sb2Te3 superlattice film enabled set and reset voltages of TRAM to be less than 40% of those of PRAM. Statistical analysis of 16kb data showed the reset voltage to be less than 1.2 V, the lowest as a TRAM test chip.
We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (Rwire) multiplied by logic gate input pin cap (Cpin), Rwire×Cpin, is identified as a major limiter of performance and power at N7. Reducing Cpin is crucial to...
Enabling a high-density ReRAM product requires: developing a cell that meets a stringent bit error rate, BER, at low program current, integrating the cell without material damage, and providing a high-drive selector at scaled nodes. We discuss ReRAM performance under these constraints and present a 16Gb, 27nm ReRAM capable of 105 cycles with BER < 7×10−5.
Endurance in filamentary RRAM is modeled in the framework of the hourglass model. Two failure modes are distinguished: (i) stochastic set failure is caused by defect generation near the bottom electrode, and (ii) resistive window changes are controlled by T-activated changes of the number of filament vacancies. Bottom electrode/oxide interface optimization is the prime knob for endurance improvement...
STT-MRAM technology has been attracting renewed attention since the embedability of a working STT-MRAM design has been demonstrated [1]. In this paper we expand on the versatility of STT-MRAM by demonstrating the conversion of a standard STT-MRAM cell to a One Time Programmable (OTP) anti-fuse cell. Both designs are integrated at the Mbit level on a single chip using the same magnetic stack, processing...
We demonstrate sub-5nm filament based electrochemical metallization RRAM with self-limited program in a reliable and controllable manner. This RRAM removes the necessity for any external current compliance in a 1TnR (1S1R) architecture. Furthermore, we report a novel technique to amplify RRAM's intrinsic ON/OFF resistance ratio by a factor of >104, which offers significant cell-, circuit- and system-level...
We demonstrate a self-rectifying, compliance-free, BEOL CMOS-compatible, resistive switching memory device, with nonfilamentary switching mechanism, forming-free operation, analog switching behavior and excellent device to device operation uniformity, down to the smallest device size. The cells have a reset switching current density of ∼0.3MA/cm2 (and ∼10x lower set current). This corresponds to ∼5uA...
Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.
We report a record setting low NMOS contact Rc of 2e−9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e−9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity...
A test circuit for studying Electromigration (EM) effects under realistic high frequency AC stress was implemented in a 32nm High-k Metal Gate (HKMG) process. Four different stress patterns (DC, pulsed DC, square AC and real AC) can be generated using on-chip circuits. Local heaters are used to raise the die temperature to >300°C for accelerated testing. Experiment results over 52.7 hours show...
A low-power 2Mb ReRAM macro was developed in 90 nm CMOS platform, demonstrating lower power data-writing (x1/7) and faster data-reading (x2∼3) as compared to a conventional flash. The memory window at −6σ for 10 years was confirmed with a high-speed 1-bit ECC considering operating temperature ranging from −40 to 85 °C, where the worst conditions are high-temperature (85°C) “Off” writing and low-temperature...
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