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We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III–V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high Ion/Ioff ratio over 107 and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found...
In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction...
High voltage I/O FinFET device optimization for a 16nm system-on-a-chip (SoC) technology is presented. After careful optimization through high electric field (E-field) mitigation by junction engineering, I/O FinFET devices with leakage current reduction by 1∼2 orders, hot carrier injection (HCI) lifetime improvement by 2.8×/1.2× for N- and PMOS, respectively, and junction breakdown voltage (Vbd) improvement...
3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint...
3D sub-system integration of logic and DRAM with TSV is desirable for wide memory bandwidth and reduced power for mobile applications. However, its manufacturing cost, along with testing and heat dissipation, remains to be outstanding issues. A new integration technology platform, InFO, is proposed to address it. In this paper, we compare three main 3D integration architectures: InFO_PoP, FC_PoP and...
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