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In this paper, improvement in the RF performance of a conventional LDMOS transistor on silicon-on-insulator (SOI) is investigated by incorporating trenches in the drift region and we propose a lateral trench RF LDMOS device. The proposed structure consists of three trenches built in the n-drift region. A single vertical gate is placed centrally in the trench between p-body region thus forming dual...
Rapid growth in the cache sizes of Chip Multiprocessors (CMPs) to support high performance applications will lead to increase in wire-delays and unexpected access latencies. NUCA architectures help in managing the capacity and access time for such larger cache designs. Static NUCA (S-NUCA) has a fixed address mapping policy whereas dynamic NUCA (D-NUCA) allows blocks to relocate nearer to the processing...
The guard zone G (of width r) of a simple polygon P is a closed region consisting of a set of straight line segments and circular arcs (of radius r) bounding the said polygon such that there exists no pair of points p (on the boundary of P) and q (on the boundary of G) having their Euclidean distance d(p, q) less than the specified value r. In this paper we have designed a cost-optimal (parallel)...
Next generation data processing unit requires high computational speed with minimum power consumption. The current technology which is driven by scaled CMOS architecture, depends on electrical charge to create or hold one of the two states — “on” or “off”. Today's data processing unit contains many such devices to build and store electric charges, thereby creating excessive heat component within the...
Image fusion is a technique to combine multiple images from a single sensor or multiple sensors into a single composite image without introducing artifacts. This paper presents a novel implementation of Laplacian pyramid image fusion on field programmable gate array (FPGA). Real time image fusion using pyramid decomposition is achieved by utilizing re-usable memory architecture and parallelisation...
Scan based Design for Testability structures are highly vulnerable to unauthorized access to the internal signals of a chip. This paper proposes a secure scan based design which prevents this unauthorized access without any compromise in the testability. The proposed secure architecture employs unique keys for each test vector. These unique keys are generated by a linear feedback shift register and...
To maintain the ever increasing demand for compaction as well as performance, 3D ICs were introduced. They have some additional advantages over their 2D counterparts in various aspects like heterogeneous integration, higher frequency, lesser interconnect length and increased bandwidth. Testing of core-based dies in 3D-SOCs poses many new challenges. This paper describes an automated post-bond core-based...
Digital Video Broadcasting (DVB-S2) is a digital television broadcast standard which is introduced as a successor for the DVB-S system. This standard is compatible with multiple input protocols (IP, MPEG-2, MPEG-4) which are either encapsulated in transport stream or generic stream. This encapsulation feature makes it possible to support voice, video as well as data known as the triple play. This...
This paper presents a 2.47 GHz capacitively transduced micromechanical disk resonator based on a Wine Glass mode of vibration. An ultra nano-crystalline diamond (UNCD) material has been used to achieve high frequency-quality factor (f.Q) product for RF applications, since this material provides highest young's modulus up to 1000 GPa and therefore highest acoustic velocity of 15000 m/s. Mode shape...
Voltage references are very essential components of analog VLSI circuits. A reference source is expected to remain constant against supply voltage, temperature and process parameter variations. The forward voltage drop across junction diode exhibits a negative temperature dependence of about 2mV/°C, which is compensated by a suitably scaled proportional to absolute temperature (PTAT) component to...
Efficient routing and cross-contamination minimization are two interrelated challenging areas in Digital Microfluidic Biochip (DMFB). This paper proposes a two phase heuristic technique for routing droplets on a two-dimensional DMFB. Initially it attempts to route maximum number of nets in a concurrent fashion depending on the evaluated value of a proposed function named Interfering Index (IInet)...
Vibrational energy harvesters (VEH) are increasingly becoming the favourite approach towards making self sustained low power systems. However, obtaining frequencies close to those of ambient vibrations has been a challenge. In the current work we have proposed a novel design of the piezoelectric-VEH (P-VEH) consisting of a micro-machined thick silicon proof mass suspended with quad-beams carved out...
This paper presents characterization of low operating voltage, high speed and power efficient comparator used as a basic building block in speed optimized Analog to Digital Converters (ADC), such as flash ADC. Overall performance of any ADC in terms of speed, resolution and power consumption highly depends on the underlying comparator being used. In this paper, better structure of comparator is implemented...
These days, in emergency, multiple assay operations are required to be performed at parallel. Area of a given chip as a constraint, how efficiently we can use the chip and how much parallelism can be built-in are the objectives of this paper. A typical application of an assay may characterize a sample where, say only one type of reagent and multiple samples have been considered, or vice versa, and...
Semi-Conductor Laboratory (SCL) Fab. has been upgraded to 8" wafer fab to support 180 nm CMOS process made available by M/s. Tower Semiconductor Ltd, Israel. This tutorial describes SCL foundry process features and capabilities. The tutorial will cover SCL Fab base line technology features, analog process modules, digital standard cell library for core and I/Os and memory modules. End to end...
In this work, novel layouts of a 4:1 CMOS transmission gate multiplexer are presented. The proposed layouts are realized by following the design rules for 45 nm and 90 nm CMOS processes, with a supply voltage of 1.2 V. Both layouts are designed using two different routing strategies — using only one metal layer, and using two metal layers. The power dissipation and area are noted and compared in all...
This work presents a design of temperature compensated and supply regulated current reference circuit with reduced process variation at low supply voltage of 1.5 V. The supply regulation of the proposed circuit is improved by using a regulated cascode technique together with an error amplifier in the CTAT (complementary to absolute temperature) circuit. The temperature compensation is achieved by...
Vibration energy harvesting is gaining attention due to abundance of vibration energy at most places and ability to generate power MEMS devices from microwatts to few millwatts. Piezoelectric energy harvesters are the most suitable for vibration energy harvesting due to simplicity in design, operation and fabrication in MEMS technology. Cantilever fixed from one end and seismic mass on the free end...
The CORDIC (COrdinated Rotation DIgital Computer)[1] algorithm provides an efficient and accurate platform to compute various trigonometric, linear and non-linear functions using only shift-add operations. This paper presents the implementation of CORDIC algorithm on a configurable architecture to port various transforms which forms the heart of image and signal processing applications. We shall demonstrate...
With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH)...
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