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The paper addresses an attempt to perform dynamic timing simulations of complex mixed signal IP's. The targeted IP is a memory and uses its behavioural model; the idea spans from checking the presence of IO Path delays and timing checks viz. setup, hold, recovery, removal, width etc, and validating the impact on the IP behaviour. The methodology is developed and validated on UVM semantics; the eco-system...
There are two main directions in the development of modern microprocessor architectures used for System on Chip: low Power consumption and high performance. The paper presents the method for enhancing LEON3 processor IP core with superscalar ability for high-performance and low-power systems. As compared to the original LEON3 IP core, the proposed super scalar design executes is up to two instructions...
Hardware IP design verification is performed using exhaustive random stimuli, while incorporating a coverage driven flow. On the other hand, system-on-chip (SoC) verification methodologies, sometimes, use a directed C-based verification approach to validate the functionality of the design. There is no significant randomization exercised in this process. Reuse of IP testbench components for SoC verification...
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