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For high end design, delay test becomes increasingly important. The paper proposes a technique to synthesize fully delay testable circuit without any additional control input. Our proposal is based on covering each ROBDD node by Invert-And-Or elements. We have shown that the generated circuit is fully testable either by robust tests or by validatable non-robust tests.
Accuracy of any diagnosis algorithm depends on the test set used. Test that is able to distinguish more fault pairs is better suited for aiding diagnosis. Standard detection test set is generated to detect faults using less number of test patterns. It is unable to distinguish many fault pairs. To distinguish pairs, more patterns are required that consumes ATE memory and time. In this work we devised...
This work targets the challenges to design with uncertainty in QCA architecture via characterization of fabrication faults caused due to particular cell displacement in the QCA logic circuit. One of the worst kind of fault to remove is input generated transient fault, called single event upset (SEU). To show the unpredictability of QCA circuits under such faults, the correct input vectors are filtered...
With the increasing complexity of VLSI circuits and systems, their testing is becoming increasingly complex and time consuming. Apart from affecting the design turn-around time, it poses severe challenges to the test engineers in terms of meeting the power-budget and temperature limit of the chip. Power consumption during test is often much higher than in normal mode of operation. Increasing temperature...
With the widespread use of applications like internet banking, secured communication, emails, etc. information security is important concern. Security of information depends on implementation of cryptographic algorithm and its complexity to solve in reverse direction. However, with the use of current high speed computational resources it is possible to carry out brute-force attack and various other...
QCA (Quantum-dot Cellular Automata) is the promising future nanotechnology for computing. In QCA, the cells must be aligned properly at nano scales for proper functioning. Defects may occur in synthesis and deposition phase. So the defect analyses and testing cannot be ignored. This paper presents a survey on QCA basics, defect characterization and various testing aspects of QCA.
Temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a particle swarm optimization (PSO) based test pattern generation strategy has been proposed for BIST environment...
Increase in design complication for current and future era of microelectronics technologies and mechanisms used for data transmission leads to an increased sensitivity to bit-flip errors. As we know, multiple cores are built in a single system on chip (SoC) and to test that SoC, test vectors are transferred from automatic test equipment (ATE) via serial communication link. Now if there is a defect...
Traditionally BIST is most widely used testing methodology because of its online and at speed testing capability. The conventional BIST suffers from hardware overhead due to the presence of on-chip test blocks such as TPG, MISR, ROM and ORA. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the first flops of scan chains as TPG and...
The present work deals with a fault tolerant approach to design the test structure for detecting the fault of cache in chip multiprocessors (CMPs). Fault detection is simplified using a 2-state 3-neighborhood null boundary cellular automata (CA). This has been elaborated in the earlier work of present authors. Self correcting property, however, has been found only in a 5-neighborhood CA and not in...
Scan based Design for Testability structures are highly vulnerable to unauthorized access to the internal signals of a chip. This paper proposes a secure scan based design which prevents this unauthorized access without any compromise in the testability. The proposed secure architecture employs unique keys for each test vector. These unique keys are generated by a linear feedback shift register and...
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