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As scan compression matures, the focus is changing from delivering QoR to other pressing requirements like hierarchical DFT implementation, pin-limited test and enabling high speed shifting of scan chains. Combinational compression schemes have had great success in the last decade in delivering a solution that provided a fast transition from traditional scan based test to compression based test. In...
The size and complexity of system-on-chip (SoC) design is growing rapidly as more and more IPs/features/functions are put into single die to reduce overall system development cost. It significantly increases SoC verification challenges in recent time due to high degree of integration of complex IPs. In this paper we will be discussing different verification strategies in different areas of verification...
In this work, novel layouts of a 4:1 CMOS transmission gate multiplexer are presented. The proposed layouts are realized by following the design rules for 45 nm and 90 nm CMOS processes, with a supply voltage of 1.2 V. Both layouts are designed using two different routing strategies — using only one metal layer, and using two metal layers. The power dissipation and area are noted and compared in all...
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