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We report the fabrication and the characterization of Tunnel FETs fabricated on SiGe-On-Insulator with a High K Metal Gate (HKMG) CMOS process. The beneficial impact of low band gap SiGe channel on ID(VG) characteristics is presented and analyzed: compressive Si0.75Ge0.25 enables to increase by a factor of 20 the saturation currents, even at small gate length (LG=50nm). This large gain is due to the...
This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect transistor (TFET) using compressively strained Si0.45Ge0.55 on Si. Introducing a counter doped pocket at the source tunnel junction in combination with a selective and self-adjusted silicidation to enlarge the tunneling area enables line tunneling aligned with the gate electric field which results...
In this work, the impact of the diameter on vertical nanowire Tunnel FETs analog parameters is evaluated experimentally and by numerical simulation, comparing two different source compositions, one with Si and another with Si73Ge27. The SiGe source device presents a higher tunneling current when compared with the Si source device, resulting in an increase of both transconductance (gm) and output conductance...
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