The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
For the first time, we report the operation of Single Electron Transistors (SETs) and Single Hole transistors (SHTs) up to 350K from Q-gate CMOS transistors at ultimate scaling. These results are obtained with gate lengths (LG) scaled down to 10nm and ∼3.4nm diameter silicon nanowires (Si-NWs). The SETs and SHTs exhibit Coulomb oscillations in the nanoampere range up to 350 K which can be amplified...
The impact of nanowire (NW) height and Si0.7Ge0.3:B source-drain (S/D) on the performance of p-type trigate NW is presented. We show that an increase in Si NW height from 14.5nm to 24nm generates up to +30% enhancement in hole effective mobility for a 13nm NW width. Effectiveness of Sio.7Geo.3:B S/D is then discussed for a wide range of NW width (13nm<W<218nm) and height (11nm<HNw<24nm)...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.