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Braun multiplier is one of the parallel array multipliers, which is used for unsigned numbers multiplication. This paper aims at an optimization of power and delay of Braun multiplier by using bypassing technique and modification of adders. The dynamic power of a multiplier can be reduced by using bypassing techniques and delay can be reduced by replacing ripple carry adder in the last stage of full...
The Fast Fourier Transform (FFT) and its inverse (IFFT) are very important algorithms in digital signal processing and communication systems. Radix-2 FFT algorithm is the simplest and most common form of the Cooley-Tukey algorithm. Radix-22 FFT algorithm is an attractive algorithm having same multiplicative complexity as radix-4 algorithm, but retains the simple butterfly structure of radix-2 algorithm...
In digital VLSI, power dissipation has become a prime constraint. Many design architecture and techniques have been developed to reduce power dissipation. In this paper implementation of combinational circuits such as logic gates, adders and multipliers in Gate diffusion input (GDI) technique and its comparison with other logic styles is presented. This technique allows reduce power consumption, transistor...
The key problems in designing of VLSI circuits are high power consumption, larger area utilization and delay which affect the speed of the computation and also results in power dissipation. In general speed and power are the essential factors in VLSI design. For solving the issues, a new architecture has been proposed. In the proposed system, the two high speed multipliers, Modified booth multiplier...
Modular multiplication finds the major role in RSA Cryptography and Elliptical Curve Cryptography. Timing analysis measures the delay along the various timing paths and verifies the performance and operation of the design. We have implemented a 256-bit Modular multiplier using Montgomery Reduction Algorithm in VHDL. The output of the Montgomery multiplier is Z=X∗Y R−1 mod M. Both RSA key generation...
Multiplication is an important function in arithmetic operations. A CPU devotes a considerable amount of processing time in performing arithmetic operations. Multiplication requires substantially more hardware resources and processing time than addition and subtraction. Along with the speed its precision also plays a major role. Floating point multipliers provide required precision and they tend to...
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistorlevel modification in BEC-1 converter to significantly reduce the area and power of the CSLA. Based...
Multipliers with high speed are essential of digital applications for example signal processing. A new architecture of multiplier-and-accumulator (MAC) was proposed for high-speed arithmetic. By combining multiplication with accumulation the performance was improved. In Modified booth algorithm technique the modified booth encoder will reduce the number of partial products. Even in general purpose...
This paper provides a new design methodology to improve the efficiency of a parallel dual core cryptoprocessor for computing pairings over Barreto Naehrig (BN) curves. The proposed design is specifically optimized for Field Programmable Gate Array Platforms(FPGA). We explore the inbuilt features of an FPGA device to improve the efficiency of a cryptoprocessor for computing 128-bit secure pairings.
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