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Modular multiplication finds the major role in RSA Cryptography and Elliptical Curve Cryptography. Timing analysis measures the delay along the various timing paths and verifies the performance and operation of the design. We have implemented a 256-bit Modular multiplier using Montgomery Reduction Algorithm in VHDL. The output of the Montgomery multiplier is Z=X∗Y R−1 mod M. Both RSA key generation...
This paper provides a new design methodology to improve the efficiency of a parallel dual core cryptoprocessor for computing pairings over Barreto Naehrig (BN) curves. The proposed design is specifically optimized for Field Programmable Gate Array Platforms(FPGA). We explore the inbuilt features of an FPGA device to improve the efficiency of a cryptoprocessor for computing 128-bit secure pairings.
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