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Dataflow applications have proven to be well-suited for hardware implementation due to their intrinsic pipelined nature. Furthermore a wide range of algorithms, ranging from image analysis to map-reduce tasks, can be expressed using this paradigm. At the same time Field Programmable Gate Arrays (FPGA) start to be employed as hardware accelerators also in high-end systems coupled with General Purpose...
Packet classification is used in network firewalls to identify and filter threats or unauthorized network access at the application level. This is realized by comparing incoming packet headers against a predefined rule set. Many solutions to packet classification are available, but most of these solutions exploit some features of the rule set in order to minimize the memory footprint of rule set storage...
Dynamically Reconfigurable Systems (DRS) allow hardware logic to be partially reconfigured while the rest of the design continues to operate. For example, the Auto Vision driver assistance system swaps video processing engines when the driving conditions change. However, the architectural flexibility of DRS also introduces challenges for verifying system functionality. Using Auto Vision as a case...
Multiply-add operations form a crucial part of many digital signal processing and control engineering applications. Since their performance is crucial for the application-level speed-up, it is worthwhile to explore a wide spectrum of implementations alternatives, trading increased area/energy usage to speed-up units on the critical path of the computation. This paper examines existing solutions and...
The main contribution of this paper is to present a new FPGA architecture for the Hough transform that identifies straight lines in a binary image. Recent FPGAs have hundreds of embedded DSP slices and block RAMs. For example, Xilinx Virtex-6 Family FPGAs have a DSP48E1 slice, which is a configurable logic block equipped with fast multipliers, adders, pipeline registers, and so on. They also have...
Research efforts in Evolvable Hardware allowed to prove how it is possible to adopt a radically alternative approach to the synthesis of hardware circuits by drawing inspiration from natural selection and evolution. In order to move these achievements to a new level, however, we need more sophisticated tools and upport for experimenting with new structures and devices. This paper moves a first step...
This paper proposes a low-power, high-speed architecture of a reconfigurable root-raised cosine (RRC) filter which serves as a major component of a digital up converter (DUC). The proposed RRC filter can be reconfigured at any time to suit one of three different interpolation factors and one of two different roll-off factors pertaining to various modern wireless communication standards. The fact that...
OFDM (Orthogonal frequency division multiplexing) is an efficient modulation scheme for wide-band digital communications and applications ranging from modems to next-generation high-speed wireless data communications[9]. Several enhancements of the OFDM have been proposed to reduce the complexity and power consumption of the transceiver while maintaining the performance. The goal of this paper is...
In this paper we describe a hardware implementation, of the MPI-2 RMA communication library primitive, devoted to a distributed Multi Processing Reconfigurable System on Chip (MP-RSoC). We designed a platform able to process communications over a custom heterogeneous MP-RSoC using our hardware MPI-2 RMA communication primitives. To implement these primitives, we have conceived a scalable Network on...
An FPGA router is developed using both the PathFinder and A* algorithms. Instead of the popular routing channel and rack model that is widely adopted by the research community, a modified routing model based on the architecture description for Xilinx devices (XDLRC) is applied. As a result, the proposed router works for any real device with an XDLRC description, which makes it a good candidate for...
IP lookup problem involves searching the input IP address for a matching IP prefix in the routing table. Hardware-accelerated IP lookup engines based on various data structures such as balanced tree structures have been proposed over the years. In tree-based approaches, as the size of the tree increases, large off-chip memory has to be used. In addition, the linear growth of wire length with respect...
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