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Performance of photovoltaic systems greatly depends on climate conditions. Apart from values of solar radiation, its variations can also have an influence on energy yield from a PV-system. In less favourable climate conditions (e.g. in central Europe), highly varying radiation is very frequent and the electrical converters (i.e. inverters, DC-DC converters) should be able to follow the irradiance...
This paper deals with the monolithic integration of switching cells that are used in power electronics for the realization of static power converters. The aim of the monolithic integration of the power switching cells is to suppress wire bonding in order to improve electrical performance as well as reliability of power modules intended for medium power applications. Within this context, the single...
In the paper we consider architecture of an analog dual delay locked loop (DLL). It uses an simply-implementable coarse delay line to push the loop close to lock state, and a fine programmable delay line to make small adjustments to the output phase. Both coarse- as well as fine-delay line are implemented as a cascades of variable-delay elements based on single-ended Schmitt triggers. For the correction...
The inverter is the key element in grid-connected photovoltaic systems. Measurements of inverter efficiency should take into account two phenomena: the DC/AC conversion and Maximum Power Point (MPP) tracking process.
We report on the design and measurements of a prototype integrated circuit structure implemented in CMOS 180 nm technology and dedicated for readout of silicon pixel detectors. The prototype structure contains 16 channels, which are built of a charge sensitive amplifier and a main amplifier stage. We present both, the design procedure of the readout front-end electronics based on an inverter amplifier...
Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is breaking the link between dynamic power and data...
This paper addresses the problem of generating non-overlapping clock phases for switched capacitor circuits at more than 1 GHz clock frequency. A simple clock phase generator providing two non-overlapping phases with low values of RMS period jitter, RMS jitter of phases' widths and phase shift of 180 degrees is proposed. The circuit relies on a back-to-back inverter structure. Simulation results over...
The paper describes structure and simulation results of the novel ring oscillator designed in UMC CMOS 0.18 µm (1.8 V). Frequency generated by the oscillator is tuned by scaling the supply voltage, additionally ring length is digitally controlled. Presented ring oscillator has very wide tuning range (250 MHz–2.1 GHz) with small current consumption (34–689 µA).
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