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In System on Chip, buses and point to point links are used as a communication infrastructure between one IP to another, but these cannot provide efficient interconnect from performance point of view. So NoC architecture was proposed to provide communication in multiprocessor SoC and overcome the limitations. This paper has implemented a 5-port 32-bit and 64-bit router architecture using wormhole routing...
Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel Binary divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary...
Evolutionary Algorithms (EA) are used in many optimization problems such as the Artificial Neural Networks (ANN). But the main challenging issue of using these algorithms is the time taken for computing the function value, implementation and verification of hardware architecture design. In this paper we propose to implement the architecture design of Back Propagation Neural (BPN) networks using Very...
Parallel computing operates on the principle that large problems can often be divided into smaller ones, which are then solved concurrently to save time (wall clock time) by taking advantage of non-local resources and overcoming memory constraints. The main aim is to form a cluster oriented parallel computing architecture for MPI based applications which demonstrates the performance gain and losses...
Multiplication is a significant process in digital signal processing algorithms. These algorithms involve large number of multiplications, which is time consuming. In digital signal applications time is more important as compared to accuracy. In this paper a simple and efficient architecture of multiplier is proposed which uses adders, shifters, encoders and decoder etc. that consume less area, time...
Semiconductor memories most specifically Static Random Access Memories (SRAMs) are becoming very popular in today's System-On-Chip (SOCs). Memories become more susceptible to faults when the complexity of these memories increase as the technology shrinks. In order to detect these faults, March algorithm has been widely used. This detection of faults in SRAM has been a time consuming process. Hence...
In this paper analysis of noise margin and power dissipation of a novel low power proposed 8T SRAM cell has been reported. In the proposed structure two voltage sources are connected with the Bit line and the other connected with the Bit bar line are used in order to reduce voltage swings at the output nodes of bit and bit bar line during the write operation. Static noise margin values have been calculated...
Universal asynchronous receiver transmitter, abbreviated DART is a integrated circuit used for serial communications over a computer or peripheral device serial port. DARTs are now commonly included in microcontrollers. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods (such as differential signaling...
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