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Junction strategies for FINFETs and high mobility channel devices in 1x nm node are discussed. Doping conformality and doping damage control are the keys for high performance scaled FINFETs. Damage-less conformal fin doping can be provided by Self Regulatory Plasma Doping (SRPD) process, based on radical absorption in low energy plasma and subsequent drive-in anneal. SRPD demonstrates 20% Ion gain...
To achieve high drive current for III–V Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) in future technology nodes, potential performance bottlenecks such as high series resistance need to be addressed. In this paper, we review several self-aligned metallization technologies available for reducing the source/drain series resistance in planar and multiple-gate III–V MOSFETs. Novel approaches...
The scaling of Schottky barrier (SB)-MOSFETs is investigated experimentally and by simulations for devices with minimum gate length as small as 20nm. The results reveal that the scaling of SB-MOSFETs with undoped silicide contacts and thus with fairly large SB has severe limitations. In contrast to normal MOSFETs, the smaller SB transistors provide lower currents due to the increasing overlap of the...
Epitaxial growth of Ni germanosilicide on relaxed SiGe (30% Ge content) substrate has been achieved by using 3 nm Al interlayer. This epitaxial layer shows a very good uniformity and smooth interface and surface. The epitaxial layer and the SiGe substrate match very well and no misfit dislocation is found at the interface.
The profiles and J-V characteristics of P- and/or chalcogen (S, Se, or Te)-introduced Ge substrates and NiGe/Ge diodes have been investigated for a Ge nMOSFET with a NiGe source/drain. We found that chalcogen and P co-introduction caused a greater increase in the number of electrons in Ge than only P introduction. Moreover, P introduction and P and chalcogen co-introduction resulted in lower (higher)...
In this paper, we focus on the electrical characteristics of the partially insulating oxide (PiOX) junctionless vertical MOSFET (JLVFET) and PiOX junction vertical MOSFET (JVFET) through computer simulations. It is clear that the PiOX JLVFET process is simple due to the absence of the source/drain (S/D) implantation and annealing, thereby reducing the fabrication cost, in whereas the PiOX JVFET needs...
Formation of heavy C and/or P doping Si alloy with a strain and/or low resistivity in FinFET S/D having only {110} plane on fin sidewall poses a challenge because, if the CVD selective epitaxy typically used in recent S/D process integration is employed, it is extremely difficult to grow heavily doped Si alloys with defect-free microstructure on {110} crystallographic plane. We propose the combination...
A Mn doped ZnO (MZO) film was prepared on n-GaN coated sapphire substrate, followed by post-deposition annealing at 700 °C, thus an n-n heterojunction light-emitting diode (LED) was fabricated, and red electroluminescence (EL) at a low voltage was realized. The n-MZO/n-GaN heterojunction shows a rectification ratio of ∼ 2.0 × 105 at ± 2 V and a dark current of 3.5 nA at −2 V. The n-MZO/n-GaN heterojunction...
Laser anneal (LA) is one of major millisecond anneal techniques (MSA) for forming ultra-shallow and highly activated junctions. There are two major commercially available laser anneal systems which are called laser spike annealing (LSA) and dynamic surface annealing (DSA) respectively. LSA and DSA are quite different in terms of laser source, wavelength, scanning mode and so on, their hardware and...
Residual damage in ‘low-dose’ implanted and ‘high-temperature’ annealed Si have not been studied well due to lack of characterization technique and awareness of its risk for device degradation. In this study, we detected and characterized residual damage, which is existed in low-dose (1013cm−2) As implanted Si after high-temperature (1100°C) RTA in N2 and O2 mixed atmosphere. The characterization...
In this paper, we use the junctionless (JL) technology to design both JL middle-gate vertical MOS (JLMGVMOS) and JL pseudo tri-gate VMOS (JLPTGVMOS) for performance comparison on analog metrics. According to TCAD simulations, the JLPTGVMOS devices demonstrate excellent characteristics, such as high transconductance (gm), transconductance generation factor (gm/Id), and voltage gain Avi, when compared...
Strained silicon germanium (sSiGe), as channel materials, has received a lot of attention due to its high hole mobility [1]–[4]. sSi/sSiGe/sSOI heterostructure substrate [5]–[8] takes the advantages of the tensile strained Si layer, and thus can increase the critical thickness for pseudomorphically grown SiGe with high Ge concentration. In this work, QW p-MOSFETs [9]–[11] on sSi/sSi0.5Ge0.5/sSOI substrate...
Band alignments of high-k dielectrics such as atomic layer deposition (ALD) grown HfO2 and Al2O3 with different thicknesses on SiO2/Si stack are investigated by X-ray photoelectron spectroscopy (XPS). The band offsets at HfO2/SiO2, Al2O3/SiO2 and SiO2/Si interfaces are found to vary with physical thickness of high-k dielectric. Concepts of gap states and charge neutrality level (CNL) are employed...
Embedded SiGe or SiGe:B (e-SiGe or e-SiGe:B) PMOS source/drain (S/D) is widely used in advanced CMOS technology. However, with germanium (Ge) content increase, it becomes more and more challenging and critical to control defect and stress relaxation. In the present work, a groove-like surface defect of selective epitaxy SiGe was reported, which can be observed both on blanket wafer and device wafer...
An asymmetric Schottky and P-N junction source/drain MOSFET contains a conventional P-N junction and a hybrid junction for the source and drain or vice versa. Owing to the asymmetric source/drain structure, this device could be used in two different situations: Schottky-junction source MOSFETs and Schottky-junction drain MOSFETs. Performances of MOSFETs featuring a gate length of 100 nm with Schottky-junction...
With the continued scaling of CMOS devices down to 32nm node and beyond, device performance is very sensitive to the lateral diffusion mechanisms influencing the effective channel length. Tools are thus, required to measure with sufficient resolution and accuracy the carrier distribution. Scanning spreading resistance microscopy (SSRM) has evolved as a successful carrier-profiling technique with sub-nm...
Vacancy-type defects in gas cluster ion-implanted Si were probed by monoenergetic positron beams. The acceleration energy of Ar-ion clusters ranged between 20 – 60 keV, and the mean cluster size was 2×103 atoms. Doppler broadening spectra of the annihilation radiation were measured, and the vacancy-rich region was found to localize at a depth of 0 – 13 nm. Two different defect species were found to...
In this work, we propose an improved small signal equivalent capacitance-voltage (C-V) model to eliminate frequency dispersion in measurement for the AlGaN/GaN heterostructure, and then we calculate the trap density in the buffer layer. Compared with photoluminescence (PL) and high resolution X-ray power diffraction (HRXRD) data, it reveals that the main component of trap is made up of the point defect...
A new conformal and damage free doping technique (monolayer doping, MLD) has been demonstrated on FinFETs with good control of short channel effects down to a gate length of ∼40nm and 20nm of Wfin. Unlike conventional ion-implantation, this approach makes use of a dopant-containing precursor to uniformly assemble a monolayer of covalently bonded dopants to enable ultra-shallow junction (USJ) of ∼5nm,...
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