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The main challenge of Low Temperature (LT) Solid Phase Epitaxy (SPE) is the dopant deactivation during post activation anneal. For the first time, we demonstrate that, for LT-SPE activated Boron (B) on thin SOI substrates, B deactivation can be well controlled during post anneal at 400 °C–600 °C. This is achieved by locating the preamorphization induced end of range defects close to the Buried OXide...
Today no insurmountable obstacles are foreseen inhibiting scaling logic devices to the 10nm node. Cost effective processes and equipment sets have been developed that allow both 3-D Tri-Gate and Ultra-Thin Body SOI integration schemes to be scaled. This allows the equipment industry to focus on innovations of new material and their integration into cost effective tool sets in time for high volume...
For 28nm and beyond technology nodes it is essential to enhance carrier mobility of the devices by introducing embedded Si:C structures using new materials or structures or new implant and anneal process schemes. In this article we review and verify available information using Si:C formation through implant and anneal approach with low temperature cluster carbon and cluster phosphorous implants. We...
Millisecond annealing (MSA) has proven to be very helpful for continued scaling of CMOS through its applications in forming highly activated ultra-shallow junctions (USJ) and reducing the thermal budget for nickel silicide contact annealing. As device scaling continues, new materials are being introduced, including high-K dielectrics, metal gates, strained channels and even new channel materials,...
In this paper, we present a simulation study of short-channel characteristics of self-aligned dual-channel source/drain-tied (SA-DCSDT) MOSFETs. Two compared devices are designed, namely, the normal SA-DCSDT MOSFET and the ultimate SA-DCSDT MOSFET. According to simulation results, the DC is used to obtain a high drain saturation current, the SDT is used to get improved thermal stability, and the BOX...
Ultrashallow junctions were fabricated by chemical vapor deposition of pure boron (PureB) at 95 torr as opposed to atmospheric pressure deposition. The low pressure deposition process with hydrogen as carrier gas demonstrated to be a viable process for fabricating ideal diodes with low saturation current and no detrimental effects. The minimum deposition temperature for forming an ideal diode is 500°C...
The M4PP measurement technique has gained increased interest from the semiconductor industry for direct sheet resistance measurements on ultra thin layers and small structures/pads. Several fully automatic microRSP probing tools are today in use for in-line sheet resistance measurements on blanket and patterned wafers. Using the next generation of microRSP probing tools it will be possible to perform...
A simulation for terahertz aluminum gallium nitride (AlGaN)/gallium nitride (GaN) resonant tunneling diode (RTD) at room temperature is reported, by introducing deep-level defects into the polarized AlGaN/GaN/AlGaN quantum well. Results show that an obvious degradation in negative differential resistance(NDR) characteristic of RTD occurs when the defect density is above 106 cm−2. Finally, a RTD oscillator...
BF2+ implant was performed on Ge1−xSnx epitaxial layers where x is 0.03 or 0.053. The implant depth for BF2+ implant into Ge1−xSnx alloys is larger as compared to the same implant into Ge. It is observed that the diffusion of B during a rapid thermal annealing (RTA) is substantially suppressed by the presence of Sn. Sheet resistance measurements show that the B atoms can be activated at 400 °C in...
In this study, we review on SSRM studies on 2D carrier profiles of various devices applications including S/D engineering and failure analysis in real SRAM devices. The correlation of SSRM images with junction leakage current of nMOSs was confirmed. We also directly observed carbon (C) co-doped Si:C nMOSs, clarifying the C doping effect on phosphorous diffusion and therefore on device characteristics...
An ultra-low energy high dose B-based implant was processed after source and drain region formed and before metal sillicide contact formed for PMOS devices. B beam-line (BL) implant and plasma doping (PLAD) using either B2H6 or BF3 gases were utilized for this process. PMOS device performance showed significant improvements, including ∼70 percent lower contact resistances, similar threshold and sub-threshold...
Low temperature cluster carbon co-implantation was applied for phosphorous activation enhancement and transient enhanced diffusion (TED) suppression. The dependence of phosphorous activation and TED on 1) carbon energy, 2) dose and 3) substrate temperature have been investigated. 1) Implanted carbon depth compared with phosphorous depth was optimized for better phosphorous TED suppression and phosphorous...
We review recent progress in the application of the two-terminal diode steering element for 3D crossbar (X-bar) memory. Such architecture is emerging as one of the strong candidates for non-volatile memory to enable mobile computing with high speed, low power, and low cost. We address process, integration, and device scaling requirements of the steering element for fabricating PCRAM and metal oxide...
PLAD (plasma doping) is promising for both evolutionary and revolutionary doping options because of its unique advantages which can overcome or minimize many of the issues of the beam-line (BL) based implants. In this talk, we present developments of PLAD on both planar and 3D device structures. Comparing with the conventional BL implants, PLAD shows not only a significant production enhancement,...
Advanced junction scaling with device performance gain, leakage reduction and reduced threshold voltage (Vth) variation are critical for CMOS 28nm node and future scaling. In this paper, implant induced defect engineering for higher drive current with reduced SRAM defectivity, advanced junction formation and Vth mismatch (Vtmin) on a state-of-the-art 28nm logic flow are demonstrated and discussed.
A novel plasma based conformal doping technique was developed in this work and process characterization was conducted for arsenic doping in terms of doping conformality, residual silicon fin damage, sheet resistance and effect of doping process parameters. Doping conformality, the ratio of doping at then fin sidewall and top, was characterized by cross-section transmission electron spectroscopy (XTEM)...
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