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Fractional-N PLLs are widely used in today's communication systems. While there is a huge demand on good phase noise performance, low spurious emission is also a must. State-of-the-art simulation tools cannot simulate spurs on transistor level due to time and memory restrictions. However, the knowledge of the precise transistor level charge pump linearity is essential for any spur simulation. This...
Two architectures of 77-GHz fractional-N phase-locked loops (PLLs) for FMCW radars are presented. Both architectures show good performance in terms of phase noise with −79 dBc/Hz at 100 kHz offset frequency. To achieve this, the integration of a delay-locked loop-based frequency multiplier for the reference signal in the PLL is proposed. It exhibits very low phase noise and proves to be an excellent...
This paper presents RF and Microwave BIST system for reconfigurability of on-chip function blocks. Design of BIST for on-chip functions is demonstrated based on design of scalable LNA gain (with digitally controlled attenuators), programmable automatic oscillation amplitude control of PLL reference VCOs and dynamic EVM estimation of IQ systems. In all aforementioned applications impacts of BIST circuits...
System-level inter-Chip and intra-Chip interferences analysis and characterization is proposed. Inter-Chip noise interferences as function of wireless coupling-path attributes (wireless separation distance between emitter and receiver chips, injected power levels, Charge-Pump-Current) are characterized. At Intra-Chip level, influence of VCO-PLL inductance architecture (8-shaped topology versus O-shaped...
A fully integrated dual loop PLL with ultra-low phase noise and fast lock time is presented. The topology combines a frequency acquisition and a phase-locked hold loop. The phase-locked hold loop includes a mixer-type phase detector (PD), a 32:1 frequency divider, an active loop filter and a VCO. A 3-state phase-frequency detector (PFD) is designed for the frequency acquisition loop. The chip was...
A low cost / low power PLL for Ku-band satellite down-converters has been fabricated in SiGe:C BiCMOS process. The PLL occupies 0.5mm2 of silicon and draws less than 25mA from 2.7/3.3V supplies. It achieves state-of-art integrated phase noise performance of 1° rms and spurs level below −65dBc.
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