The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The Discrete wavelet transform (DWT) has been used in a wide range of real-time application. Algebraic integer quantization (AIQ) encoding has been proposed to represent the irrational transform basis of the wavelet transform as polynomials with integer coefficients. In this paper, we suggest to restate these polynomials to obtain simpler coefficients for both the integer coefficients and the polynomial...
In this paper, using of short-time chirp excitation for the bio-impedance measurement is discussed. The short-time chirp waveforms have at least two advantages. First, flat and wideband amplitude spectrum together with shortness of signal enable fast and adequate estimation of the object under study. Second, low power consumption with more than 90% concentration of the generated excitation energy...
A novel topology for a high speed voltage level shifter (VLS) is presented. It features a built-in short circuit current reduction which increases the speed and reduces the power consumption. Unlike the conventional VLSs, the proposed VLS does not need complex digital timing signals. The simplicity of its operation results into robustness of operation, high speed and low power. The VLS was designed...
This paper deals with the realization of a visual monitoring system for the real time detection of spatters in laser beam welding (LBW). Spatters deteriorate the corrosion resistance and the aesthetics of the welding result. Therefore, the real time detection of spatters allows providing on-line quality information about the process, thus reducing material waste in production chains. The proposed...
This paper presents a two-channel Hybrid Filter Bank (HFB) Analog-to-Digital Converter (ADC) that targets broadband digitization, for Cognitive Radio (CR) applications. The proposed architecture partitioning uses low-cost third order Butterworth analog filters and fourth order digital IIR filters. The optimization algorithm combines direct simplex search, minimax methods and a perturbation strategy...
This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in...
In this paper a novel Winner-Take-All (WTA) topology is presented which shows good trade-off between resolution and resolution speed, at the cost of some increase in power consumption. The proposed WTA is compared with other current-mode WTAs found in literature based on the same operation principle. All the topologies were designed in a 0.13µm CMOS process and characterized in terms of resolution,...
This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing six levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang...
In this paper, the design of variable fractional order differentiator (VFOD) using the infinite product expansion is presented. First, the infinite products of hyperbolic cosine and sine functions are applied to transform the VFOD design into the designs of first and second order digital log differentiators. Then, the FIR log differentiators designed by least-squares method are used to implement the...
FFT-IFFT configuration, or more generally a forward-inverse orthogonal transform pair, offers a way to implement a digital filter whose frequency-domain characteristics can be straightforwardly tuned by adjusting the complex gains of the frequency bins. Using filter banks (FBs) for the transform pair, sharp transition bands can be obtained for low-pass/bandpass/highpass type filter designs. However,...
In this paper a 10-bit, 5kHz bandwidth, continuous time ADC, which employs level-crossing sampling to convert an analog signal to a digital one, is presented. The proposed level-crossing ADC does not use any clock and sampling in time is not involved. The level-crossing ADC acquires samples only when they provide a new information about the input signal, thus dissipating power only when needed. Cadence...
Computing Euclidean Distances is a very important operation in digital communication, especially in the case of trellis coded modulation, where it is used numerously. This paper shows that a substantial reduction in complexity can be achieved in hardware processing elements for computing Euclidean Distances. A reduction in complexity down to 39% is shown compared to traditional designs. The paper...
An architecture for MDAC stages with low sensitivity to finite opamp gain is proposed, that allows designing high-precision pipeline ADCs in deep submicron technologies. The standard MDAC architecture is modified by inserting a voltage follower in the feedback path, and zero gain error is achieved if a relationship between the gain of the main opamp and of the opamp used in the voltage follower is...
Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-VT analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-VT regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized...
This paper addresses the problem of optimizing gate-level area in a pipelined Multiple Constant Multiplications (MCM) operation and introduces a high-level synthesis algorithm, called HCUB-DC+ILP. In the HCUB-DC+ILP algorithm, initially, a solution with the fewest number of operations under a minimum delay constraint is found by the Hcub-DC algorithm. Then, the area around this local minimum point...
This paper describes a low-power fully differential cyclic ADC. It utilizes a 3-bit C-2C ladder to achieve 9-bit resolution. For the 9-bit resolution the 3-bit C-2C ladder occupies 64 times less area than a binary weighted capacitance array. The operational amplifier with the slew rate detection is used in order to increase the speed of the ADC. The simulated power consumption of the ADC is 33 µW@3...
The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12–14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different...
Power consumption is an important limitation to analog-to-digital converters. The objective of this paper is to estimate a lower bound to the power consumption of successive approximation analog-to-digital converters. This is an extension of our previous work which was limited to pipelined and flash architectures. We find that the power consumption in our case is bounded by capacitor mismatch or thermal...
Deep sub-micron CMOS technologies have enabled the development of highly digital radios for wireless communications at low Gigahertz frequencies [1], [2]. Meanwhile, nanometer scale CMOS allows to push the RF frequencies to the millimeter wave frequency range. Particularly 60GHz radio has emerged as the candidate for high-data-rate (10 Gb/sec), short-distance (1 to 10m) wireless communication systems...
An empirical design optimization approach is explored for A/D-converter area efficiency. The die area consumption of commonly used ADC architectures is surveyed. Based on trends observed in a large set of empirical data, the area normalized to number of effective quantization steps is proposed as a generic measure of area efficiency. It is seen that state-of-the-art absolute area has a strong correlation...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.